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zoom2
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zoom2.h

zoom2.h 7.7 KB
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  1. /*
    2. 

  2.  * Copyright (c) 2009 Wind River Systems, Inc.
    3. 

  3.  * Tom Rix <Tom.Rix@windriver.com>
    4. 

  4.  *
    5. 

  5.  * Derived from: board/omap3/zoom1/zoom1.h
    6. 

  6.  * Nishanth Menon <nm@ti.com>
    7. 

  7.  *
    8. 

  8.  * See file CREDITS for list of people who contributed to this
    9. 

  9.  * project.
    10. 

  10.  *
    11. 

  11.  * This program is free software; you can redistribute it and/or
    12. 

  12.  * modify it under the terms of the GNU General Public License as
    13. 

  13.  * published by the Free Software Foundation; either version 2 of
    14. 

  14.  * the License, or (at your option) any later version.
    15. 

  15.  *
    16. 

  16.  * This program is distributed in the hope that it will be useful,
    17. 

  17.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    18. 

  18.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    19. 

  19.  * GNU General Public License for more details.
    20. 

  20.  *
    21. 

  21.  * You should have received a copy of the GNU General Public License
    22. 

  22.  * along with this program; if not, write to the Free Software
    23. 

  23.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    24. 

  24.  * MA 02111-1307 USA
    25. 

  25.  */
    26. 

  26. #ifndef _BOARD_ZOOM2_H_
    27. 

  27. #define _BOARD_ZOOM2_H_
    28. 

  28. 

  29. const omap3_sysinfo sysinfo = {
    30. 

  30. 	DDR_STACKED,
    31. 

  31. 	"OMAP3 Zoom2 ",
    32. 

  32. 	"NAND",
    33. 

  33. };
    34. 

  34. 

  35. typedef enum {
    36. 

  36. 	ZOOM2_REVISION_UNKNOWN = 0,
    37. 

  37. 	ZOOM2_REVISION_ALPHA,
    38. 

  38. 	ZOOM2_REVISION_BETA,
    39. 

  39. 	ZOOM2_REVISION_PRODUCTION
    40. 

  40. } zoom2_revision;
    41. 

  41. 

  42. zoom2_revision zoom2_get_revision(void);
    43. 

  43. 

  44. /*
    45. 

  45.  * IEN	- Input Enable
    46. 

  46.  * IDIS	- Input Disable
    47. 

  47.  * PTD	- Pull type Down
    48. 

  48.  * PTU	- Pull type Up
    49. 

  49.  * DIS	- Pull type selection is inactive
    50. 

  50.  * EN	- Pull type selection is active
    51. 

  51.  * M0	- Mode 0
    52. 

  52.  * The commented string gives the final mux configuration for that pin
    53. 

  53.  */
    54. 

  54. #define MUX_ZOOM2() \
    55. 

  55.  /* SDRC*/\
    56. 

  56. 	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) /* SDRC_D0 */\
    57. 

  57. 	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) /* SDRC_D1 */\
    58. 

  58. 	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) /* SDRC_D2 */\
    59. 

  59. 	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) /* SDRC_D3 */\
    60. 

  60. 	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) /* SDRC_D4 */\
    61. 

  61. 	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) /* SDRC_D5 */\
    62. 

  62. 	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) /* SDRC_D6 */\
    63. 

  63. 	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) /* SDRC_D7 */\
    64. 

  64. 	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) /* SDRC_D8 */\
    65. 

  65. 	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) /* SDRC_D9 */\
    66. 

  66. 	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) /* SDRC_D10 */\
    67. 

  67. 	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) /* SDRC_D11 */\
    68. 

  68. 	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) /* SDRC_D12 */\
    69. 

  69. 	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) /* SDRC_D13 */\
    70. 

  70. 	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) /* SDRC_D14 */\
    71. 

  71. 	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) /* SDRC_D15 */\
    72. 

  72. 	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) /* SDRC_D16 */\
    73. 

  73. 	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) /* SDRC_D17 */\
    74. 

  74. 	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) /* SDRC_D18 */\
    75. 

  75. 	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) /* SDRC_D19 */\
    76. 

  76. 	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) /* SDRC_D20 */\
    77. 

  77. 	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) /* SDRC_D21 */\
    78. 

  78. 	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) /* SDRC_D22 */\
    79. 

  79. 	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) /* SDRC_D23 */\
    80. 

  80. 	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) /* SDRC_D24 */\
    81. 

  81. 	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) /* SDRC_D25 */\
    82. 

  82. 	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) /* SDRC_D26 */\
    83. 

  83. 	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) /* SDRC_D27 */\
    84. 

  84. 	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) /* SDRC_D28 */\
    85. 

  85. 	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) /* SDRC_D29 */\
    86. 

  86. 	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) /* SDRC_D30 */\
    87. 

  87. 	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) /* SDRC_D31 */\
    88. 

  88. 	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) /* SDRC_CLK */\
    89. 

  89. 	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS0 */\
    90. 

  90. 	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS1 */\
    91. 

  91. 	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS2 */\
    92. 

  92. 	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) /* SDRC_DQS3 */\
    93. 

  93. /* GPMC */\
    94. 

  94. 	MUX_VAL(CP(GPMC_A1),		(IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
    95. 

  95. 	MUX_VAL(CP(GPMC_A2),		(IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
    96. 

  96. 	MUX_VAL(CP(GPMC_A3),		(IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
    97. 

  97. 	MUX_VAL(CP(GPMC_A4),		(IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
    98. 

  98. 	MUX_VAL(CP(GPMC_A5),		(IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
    99. 

  99. 	MUX_VAL(CP(GPMC_A6),		(IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
    100. 

  100. 	MUX_VAL(CP(GPMC_A7),		(IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
    101. 

  101. 	MUX_VAL(CP(GPMC_A8),		(IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
    102. 

  102. 	MUX_VAL(CP(GPMC_A9),		(IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
    103. 

  103. 	MUX_VAL(CP(GPMC_A10),		(IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
    104. 

  104. 	MUX_VAL(CP(GPMC_D0),		(IEN  | PTD | DIS | M0)) /* GPMC_D0 */\
    105. 

  105. 	MUX_VAL(CP(GPMC_D1),		(IEN  | PTD | DIS | M0)) /* GPMC_D1 */\
    106. 

  106. 	MUX_VAL(CP(GPMC_D2),		(IEN  | PTD | DIS | M0)) /* GPMC_D2 */\
    107. 

  107. 	MUX_VAL(CP(GPMC_D3),		(IEN  | PTD | DIS | M0)) /* GPMC_D3 */\
    108. 

  108. 	MUX_VAL(CP(GPMC_D4),		(IEN  | PTD | DIS | M0)) /* GPMC_D4 */\
    109. 

  109. 	MUX_VAL(CP(GPMC_D5),		(IEN  | PTD | DIS | M0)) /* GPMC_D5 */\
    110. 

  110. 	MUX_VAL(CP(GPMC_D6),		(IEN  | PTD | DIS | M0)) /* GPMC_D6 */\
    111. 

  111. 	MUX_VAL(CP(GPMC_D7),		(IEN  | PTD | DIS | M0)) /* GPMC_D7 */\
    112. 

  112. 	MUX_VAL(CP(GPMC_D8),		(IEN  | PTD | DIS | M0)) /* GPMC_D8 */\
    113. 

  113. 	MUX_VAL(CP(GPMC_D9),		(IEN  | PTD | DIS | M0)) /* GPMC_D9 */\
    114. 

  114. 	MUX_VAL(CP(GPMC_D10),		(IEN  | PTD | DIS | M0)) /* GPMC_D10 */\
    115. 

  115. 	MUX_VAL(CP(GPMC_D11),		(IEN  | PTD | DIS | M0)) /* GPMC_D11 */\
    116. 

  116. 	MUX_VAL(CP(GPMC_D12),		(IEN  | PTD | DIS | M0)) /* GPMC_D12 */\
    117. 

  117. 	MUX_VAL(CP(GPMC_D13),		(IEN  | PTD | DIS | M0)) /* GPMC_D13 */\
    118. 

  118. 	MUX_VAL(CP(GPMC_D14),		(IEN  | PTD | DIS | M0)) /* GPMC_D14 */\
    119. 

  119. 	MUX_VAL(CP(GPMC_D15),		(IEN  | PTD | DIS | M0)) /* GPMC_D15 */\
    120. 

  120. 	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) /* GPMC_nCS0 */\
    121. 

  121. 	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS1 */\
    122. 

  122. 	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS2 */\
    123. 

  123. 	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS3 */\
    124. 

  124. 	MUX_VAL(CP(GPMC_NCS4),		(IDIS | PTU | EN  | M7)) /* GPMC_nCS4 */\
    125. 

  125. 	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTD | DIS | M7)) /* GPMC_nCS5 */\
    126. 

  126. 	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M7)) /* GPMC_nCS6 */\
    127. 

  127. 	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M7)) /* GPMC_nCS7 */\
    128. 

  128. 	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
    129. 

  129. 	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
    130. 

  130. 	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
    131. 

  131. 	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
    132. 

  132. 	MUX_VAL(CP(GPMC_NWP),		(IDIS | PTU | DIS | M0)) /* GPMC_nWP */\
    133. 

  133. 	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
    134. 

  134. 	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
    135. 

  135. 	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTD | EN  | M0)) /* GPMC_WAIT0 */\
    136. 

  136. 	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0)) /* GPMC_WAIT1 */\
    137. 

  137. 	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M0)) /* GPMC_WAIT2 */\
    138. 

  138. 	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0)) /* GPMC_WAIT3 */\
    139. 

  139. /* IDCC modem Power On */\
    140. 

  140. 	MUX_VAL(CP(CAM_D11),		(IEN  | PTU | EN  | M4)) /* GPIO_110 */\
    141. 

  141. 	MUX_VAL(CP(CAM_D4),		(IEN  | PTU | EN  | M4)) /* GPIO_103 */\
    142. 

  142. /* GPMC CS7 has LAN9211 device */\
    143. 

  143. 	MUX_VAL(CP(GPMC_NCS7),		(IDIS | PTU | EN  | M0)) /* GPMC_nCS7 */\
    144. 

  144. 	MUX_VAL(CP(MCBSP1_DX),		(IEN  | PTD | DIS | M4)) /* LAN9221 */\
    145. 

  145. 	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTD | EN  | M0)) /* MCSPI1_CS2 */\
    146. 

  146. /* GPMC CS3 has Serial TL16CP754C device */\
    147. 

  147. 	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0)) /* GPMC_nCS3 */\
    148. 

  148. /* Toggle Reset pin of TL16CP754C device */\
    149. 

  149. 	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTU | EN  | M4)) /* GPIO_152 */\
    150. 

  150.  udelay(10);\
    151. 

  151. 	MUX_VAL(CP(MCBSP4_CLKX),	(IEN  | PTD | EN  | M4)) /* GPIO_152 */\
    152. 

  152. 	MUX_VAL(CP(SDRC_CKE1),		(IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */\
    153. 

  153. /* LEDS */\
    154. 

  154. 	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | EN  | M4)) /* GPIO_173 red  */\
    155. 

  155. 	MUX_VAL(CP(MCBSP4_DX),		(IEN  | PTD | EN  | M4)) /* GPIO_154 blue */\
    156. 

  156. 	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTD | EN  | M4)) /* GPIO_61 blue2 */
    157. 

  157. 

  158. #endif /* _BOARD_ZOOM2_H_ */
    159.