at91sam9m10g45ek.c 8.6 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stelian Pop <stelian.pop@leadtechdesign.com>
  4. * Lead Tech Design <www.leadtechdesign.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <common.h>
  25. #include <asm/sizes.h>
  26. #include <asm/arch/at91sam9g45.h>
  27. #include <asm/arch/at91sam9_matrix.h>
  28. #include <asm/arch/at91sam9_smc.h>
  29. #include <asm/arch/at91_common.h>
  30. #include <asm/arch/at91_pmc.h>
  31. #include <asm/arch/at91_rstc.h>
  32. #include <asm/arch/clk.h>
  33. #include <asm/arch/gpio.h>
  34. #include <asm/arch/io.h>
  35. #include <asm/arch/hardware.h>
  36. #include <lcd.h>
  37. #include <atmel_lcdc.h>
  38. #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  39. #include <net.h>
  40. #endif
  41. #include <netdev.h>
  42. DECLARE_GLOBAL_DATA_PTR;
  43. /* ------------------------------------------------------------------------- */
  44. /*
  45. * Miscelaneous platform dependent initialisations
  46. */
  47. #ifdef CONFIG_CMD_NAND
  48. static void at91sam9m10g45ek_nand_hw_init(void)
  49. {
  50. unsigned long csa;
  51. /* Enable CS3 */
  52. csa = at91_sys_read(AT91_MATRIX_EBICSA);
  53. at91_sys_write(AT91_MATRIX_EBICSA,
  54. csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
  55. /* Configure SMC CS3 for NAND/SmartMedia */
  56. at91_sys_write(AT91_SMC_SETUP(3),
  57. AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  58. AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  59. at91_sys_write(AT91_SMC_PULSE(3),
  60. AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
  61. AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
  62. at91_sys_write(AT91_SMC_CYCLE(3),
  63. AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
  64. at91_sys_write(AT91_SMC_MODE(3),
  65. AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  66. AT91_SMC_EXNWMODE_DISABLE |
  67. #ifdef CONFIG_SYS_NAND_DBW_16
  68. AT91_SMC_DBW_16 |
  69. #else /* CONFIG_SYS_NAND_DBW_8 */
  70. AT91_SMC_DBW_8 |
  71. #endif
  72. AT91_SMC_TDF_(3));
  73. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
  74. /* Configure RDY/BSY */
  75. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  76. /* Enable NandFlash */
  77. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  78. }
  79. #endif
  80. #ifdef CONFIG_CMD_USB
  81. static void at91sam9m10g45ek_usb_hw_init(void)
  82. {
  83. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
  84. at91_set_gpio_output(AT91_PIN_PD1, 0);
  85. at91_set_gpio_output(AT91_PIN_PD3, 0);
  86. }
  87. #endif
  88. #ifdef CONFIG_MACB
  89. static void at91sam9m10g45ek_macb_hw_init(void)
  90. {
  91. unsigned long rstc;
  92. /* Enable clock */
  93. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
  94. /*
  95. * Disable pull-up on:
  96. * RXDV (PA15) => PHY normal mode (not Test mode)
  97. * ERX0 (PA12) => PHY ADDR0
  98. * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
  99. *
  100. * PHY has internal pull-down
  101. */
  102. writel(pin_to_mask(AT91_PIN_PA15) |
  103. pin_to_mask(AT91_PIN_PA12) |
  104. pin_to_mask(AT91_PIN_PA13),
  105. pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
  106. rstc = at91_sys_read(AT91_RSTC_MR);
  107. /* Need to reset PHY -> 500ms reset */
  108. at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
  109. (AT91_RSTC_ERSTL & (0x0D << 8)) |
  110. AT91_RSTC_URSTEN);
  111. at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
  112. /* Wait for end hardware reset */
  113. while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
  114. /* Restore NRST value */
  115. at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
  116. (rstc) |
  117. AT91_RSTC_URSTEN);
  118. /* Re-enable pull-up */
  119. writel(pin_to_mask(AT91_PIN_PA15) |
  120. pin_to_mask(AT91_PIN_PA12) |
  121. pin_to_mask(AT91_PIN_PA13),
  122. pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
  123. at91_macb_hw_init();
  124. }
  125. #endif
  126. #ifdef CONFIG_LCD
  127. vidinfo_t panel_info = {
  128. vl_col: 480,
  129. vl_row: 272,
  130. vl_clk: 9000000,
  131. vl_sync: ATMEL_LCDC_INVLINE_NORMAL |
  132. ATMEL_LCDC_INVFRAME_NORMAL,
  133. vl_bpix: 3,
  134. vl_tft: 1,
  135. vl_hsync_len: 45,
  136. vl_left_margin: 1,
  137. vl_right_margin:1,
  138. vl_vsync_len: 1,
  139. vl_upper_margin:40,
  140. vl_lower_margin:1,
  141. mmio: AT91SAM9G45_LCDC_BASE,
  142. };
  143. void lcd_enable(void)
  144. {
  145. at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
  146. }
  147. void lcd_disable(void)
  148. {
  149. at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
  150. }
  151. static void at91sam9m10g45ek_lcd_hw_init(void)
  152. {
  153. at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
  154. at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
  155. at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
  156. at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
  157. at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
  158. at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
  159. at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
  160. at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
  161. at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
  162. at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
  163. at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
  164. at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
  165. at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
  166. at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
  167. at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
  168. at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
  169. at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
  170. at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
  171. at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
  172. at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
  173. at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
  174. at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
  175. at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
  176. at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
  177. at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
  178. at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
  179. at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
  180. at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
  181. at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
  182. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
  183. gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
  184. }
  185. #ifdef CONFIG_LCD_INFO
  186. #include <nand.h>
  187. #include <version.h>
  188. void lcd_show_board_info(void)
  189. {
  190. ulong dram_size, nand_size;
  191. int i;
  192. char temp[32];
  193. lcd_printf ("%s\n", U_BOOT_VERSION);
  194. lcd_printf ("(C) 2008 ATMEL Corp\n");
  195. lcd_printf ("at91support@atmel.com\n");
  196. lcd_printf ("%s CPU at %s MHz\n",
  197. CONFIG_SYS_AT91_CPU_NAME,
  198. strmhz(temp, get_cpu_clk_rate()));
  199. dram_size = 0;
  200. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  201. dram_size += gd->bd->bi_dram[i].size;
  202. nand_size = 0;
  203. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  204. nand_size += nand_info[i].size;
  205. lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
  206. dram_size >> 20,
  207. nand_size >> 20 );
  208. }
  209. #endif /* CONFIG_LCD_INFO */
  210. #endif
  211. int board_init(void)
  212. {
  213. /* Enable Ctrlc */
  214. console_init_f();
  215. /* arch number of AT91SAM9M10G45EK-Board */
  216. #ifdef CONFIG_AT91SAM9M10G45EK
  217. gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
  218. #elif defined CONFIG_AT91SAM9G45EKES
  219. gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
  220. #endif
  221. /* adress of boot parameters */
  222. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  223. at91_serial_hw_init();
  224. #ifdef CONFIG_CMD_NAND
  225. at91sam9m10g45ek_nand_hw_init();
  226. #endif
  227. #ifdef CONFIG_CMD_USB
  228. at91sam9m10g45ek_usb_hw_init();
  229. #endif
  230. #ifdef CONFIG_HAS_DATAFLASH
  231. at91_spi0_hw_init(1 << 0);
  232. #endif
  233. #ifdef CONFIG_ATMEL_SPI
  234. at91_spi0_hw_init(1 << 4);
  235. #endif
  236. #ifdef CONFIG_MACB
  237. at91sam9m10g45ek_macb_hw_init();
  238. #endif
  239. #ifdef CONFIG_LCD
  240. at91sam9m10g45ek_lcd_hw_init();
  241. #endif
  242. return 0;
  243. }
  244. int dram_init(void)
  245. {
  246. gd->bd->bi_dram[0].start = PHYS_SDRAM;
  247. gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
  248. return 0;
  249. }
  250. #ifdef CONFIG_RESET_PHY_R
  251. void reset_phy(void)
  252. {
  253. }
  254. #endif
  255. int board_eth_init(bd_t *bis)
  256. {
  257. int rc = 0;
  258. #ifdef CONFIG_MACB
  259. rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00);
  260. #endif
  261. return rc;
  262. }
  263. /* SPI chip select control */
  264. #ifdef CONFIG_ATMEL_SPI
  265. #include <spi.h>
  266. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  267. {
  268. return bus == 0 && cs < 2;
  269. }
  270. void spi_cs_activate(struct spi_slave *slave)
  271. {
  272. switch(slave->cs) {
  273. case 1:
  274. at91_set_gpio_output(AT91_PIN_PB18, 0);
  275. break;
  276. case 0:
  277. default:
  278. at91_set_gpio_output(AT91_PIN_PB3, 0);
  279. break;
  280. }
  281. }
  282. void spi_cs_deactivate(struct spi_slave *slave)
  283. {
  284. switch(slave->cs) {
  285. case 1:
  286. at91_set_gpio_output(AT91_PIN_PB18, 1);
  287. break;
  288. case 0:
  289. default:
  290. at91_set_gpio_output(AT91_PIN_PB3, 1);
  291. break;
  292. }
  293. }
  294. #endif /* CONFIG_ATMEL_SPI */