| 1234567891011121314151617181920212223242526272829303132333435363738394041424344 |
- /*
- * (C) Copyright 2010
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
- #ifndef _PPC460SX_H_
- #define _PPC460SX_H_
- #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
- /* Memory mapped registers */
- #define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */
- #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
- #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
- #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
- #define SDR0_SRST0_DMC 0x00200000
- #define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
- #define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
- #define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
- #define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
- #define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */
- #define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
- #define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
- #endif /* _PPC460SX_H_ */
|
