iomux.c 4.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166
  1. /*
  2. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/imx-regs.h>
  25. #include <asm/arch/mx51_pins.h>
  26. #include <asm/arch/iomux.h>
  27. #include <asm/arch/sys_proto.h>
  28. /* IOMUX register (base) addresses */
  29. enum iomux_reg_addr {
  30. IOMUXGPR0 = IOMUXC_BASE_ADDR,
  31. IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004,
  32. IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
  33. IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
  34. IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
  35. IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
  36. };
  37. #define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
  38. /* Get the iomux register address of this pin */
  39. static inline u32 get_mux_reg(iomux_pin_name_t pin)
  40. {
  41. u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
  42. if (is_soc_rev(CHIP_REV_2_0) < 0) {
  43. /*
  44. * Fixup register address:
  45. * i.MX51 TO1 has offset with the register
  46. * which is define as TO2.
  47. */
  48. if ((pin == MX51_PIN_NANDF_RB5) ||
  49. (pin == MX51_PIN_NANDF_RB6) ||
  50. (pin == MX51_PIN_NANDF_RB7))
  51. ; /* Do nothing */
  52. else if (mux_reg >= 0x2FC)
  53. mux_reg += 8;
  54. else if (mux_reg >= 0x130)
  55. mux_reg += 0xC;
  56. }
  57. mux_reg += IOMUXSW_MUX_CTL;
  58. return mux_reg;
  59. }
  60. /* Get the pad register address of this pin */
  61. static inline u32 get_pad_reg(iomux_pin_name_t pin)
  62. {
  63. u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
  64. if (is_soc_rev(CHIP_REV_2_0) < 0) {
  65. /*
  66. * Fixup register address:
  67. * i.MX51 TO1 has offset with the register
  68. * which is define as TO2.
  69. */
  70. if ((pin == MX51_PIN_NANDF_RB5) ||
  71. (pin == MX51_PIN_NANDF_RB6) ||
  72. (pin == MX51_PIN_NANDF_RB7))
  73. ; /* Do nothing */
  74. else if (pad_reg == 0x4D0 - PAD_I_START)
  75. pad_reg += 0x4C;
  76. else if (pad_reg == 0x860 - PAD_I_START)
  77. pad_reg += 0x9C;
  78. else if (pad_reg >= 0x804 - PAD_I_START)
  79. pad_reg += 0xB0;
  80. else if (pad_reg >= 0x7FC - PAD_I_START)
  81. pad_reg += 0xB4;
  82. else if (pad_reg >= 0x4E4 - PAD_I_START)
  83. pad_reg += 0xCC;
  84. else
  85. pad_reg += 8;
  86. }
  87. pad_reg += IOMUXSW_PAD_CTL;
  88. return pad_reg;
  89. }
  90. /* Get the last iomux register address */
  91. static inline u32 get_mux_end(void)
  92. {
  93. if (is_soc_rev(CHIP_REV_2_0) < 0)
  94. return IOMUXC_BASE_ADDR + (0x3F8 - 4);
  95. else
  96. return IOMUXC_BASE_ADDR + (0x3F0 - 4);
  97. }
  98. /*
  99. * This function is used to configure a pin through the IOMUX module.
  100. * @param pin a pin number as defined in iomux_pin_name_t
  101. * @param cfg an output function as defined in iomux_pin_cfg_t
  102. *
  103. * @return 0 if successful; Non-zero otherwise
  104. */
  105. static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
  106. {
  107. u32 mux_reg = get_mux_reg(pin);
  108. if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL))
  109. return ;
  110. if (cfg == IOMUX_CONFIG_GPIO)
  111. writel(PIN_TO_ALT_GPIO(pin), mux_reg);
  112. else
  113. writel(cfg, mux_reg);
  114. }
  115. /*
  116. * Request ownership for an IO pin. This function has to be the first one
  117. * being called before that pin is used. The caller has to check the
  118. * return value to make sure it returns 0.
  119. *
  120. * @param pin a name defined by iomux_pin_name_t
  121. * @param cfg an input function as defined in iomux_pin_cfg_t
  122. *
  123. */
  124. void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
  125. {
  126. iomux_config_mux(pin, cfg);
  127. }
  128. /*
  129. * Release ownership for an IO pin
  130. *
  131. * @param pin a name defined by iomux_pin_name_t
  132. * @param cfg an input function as defined in iomux_pin_cfg_t
  133. */
  134. void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg)
  135. {
  136. }
  137. /*
  138. * This function configures the pad value for a IOMUX pin.
  139. *
  140. * @param pin a pin number as defined in iomux_pin_name_t
  141. * @param config the ORed value of elements defined in iomux_pad_config_t
  142. */
  143. void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config)
  144. {
  145. u32 pad_reg = get_pad_reg(pin);
  146. writel(config, pad_reg);
  147. }
  148. unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
  149. {
  150. u32 pad_reg = get_pad_reg(pin);
  151. return readl(pad_reg);
  152. }