timer.c 2.3 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879
  1. /*
  2. * (C) Copyright 2009 Alessandro Rubini
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/mtu.h>
  25. /*
  26. * The timer is a decrementer, we'll left it free running at 2.4MHz.
  27. * We have 2.4 ticks per microsecond and an overflow in almost 30min
  28. */
  29. #define TIMER_CLOCK (24 * 100 * 1000)
  30. #define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */
  31. #define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */
  32. #define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
  33. #define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
  34. /* macro to read the decrementing 32 bit timer as an increasing count */
  35. #define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
  36. /* Configure a free-running, auto-wrap counter with no prescaler */
  37. int timer_init(void)
  38. {
  39. writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
  40. CONFIG_SYS_TIMERBASE + MTU_CR(0));
  41. reset_timer();
  42. return 0;
  43. }
  44. /* Restart counting from 0 */
  45. void reset_timer(void)
  46. {
  47. ulong val;
  48. writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
  49. /*
  50. * The load-register isn't really immediate: it changes on clock
  51. * edges, so we must wait for our newly-written value to appear.
  52. * Since we might miss reading 0, wait for any change in value.
  53. */
  54. val = READ_TIMER();
  55. while (READ_TIMER() == val)
  56. ;
  57. }
  58. /* Return how many HZ passed since "base" */
  59. ulong get_timer(ulong base)
  60. {
  61. return TICKS_TO_HZ(READ_TIMER()) - base;
  62. }
  63. /* Delay x useconds */
  64. void __udelay(unsigned long usec)
  65. {
  66. ulong ini, end;
  67. ini = READ_TIMER();
  68. end = ini + USEC_TO_COUNT(usec);
  69. while ((signed)(end - READ_TIMER()) > 0)
  70. ;
  71. }