gth2.h 6.0 KB

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  1. /*
  2. * (C) Copyright 2005
  3. * Thomas.Lange@corelatus.se
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * This file contains the configuration parameters for the gth2 board.
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. #define CONFIG_MIPS32 1 /* MIPS32 CPU core */
  29. #define CONFIG_GTH2 1
  30. #define CONFIG_AU1X00 1 /* alchemy series cpu */
  31. #define CONFIG_AU1000 1
  32. #define CONFIG_MISC_INIT_R 1
  33. #define CONFIG_ETHADDR DE:AD:BE:EF:01:02 /* Ethernet address */
  34. #define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
  35. #define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */
  36. #define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */
  37. #define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */
  38. #define CONFIG_BAUDRATE 115200
  39. /* valid baudrates */
  40. #define CFG_BAUDRATE_TABLE { 115200 }
  41. /* Only interrupt boot if space is pressed */
  42. /* If a long serial cable is connected but */
  43. /* other end is dead, garbage will be read */
  44. #define CONFIG_AUTOBOOT_KEYED 1
  45. #define CONFIG_AUTOBOOT_PROMPT "Press space to abort autoboot in %d second\n"
  46. #define CONFIG_AUTOBOOT_DELAY_STR "d"
  47. #define CONFIG_AUTOBOOT_STOP_STR " "
  48. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  49. #define CONFIG_BOOTARGS "panic=1"
  50. #define CONFIG_EXTRA_ENV_SETTINGS \
  51. "addmisc=setenv bootargs $(bootargs) " \
  52. "ethaddr=$(ethaddr) \0" \
  53. "netboot=bootp;run addmisc;bootm\0" \
  54. ""
  55. /* Boot from Compact flash partition 2 as default */
  56. #define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm"
  57. /*
  58. * BOOTP options
  59. */
  60. #define CONFIG_BOOTP_BOOTFILESIZE
  61. #define CONFIG_BOOTP_BOOTPATH
  62. #define CONFIG_BOOTP_GATEWAY
  63. #define CONFIG_BOOTP_HOSTNAME
  64. /*
  65. * Command line configuration.
  66. */
  67. #include <config_cmd_default.h>
  68. #define CONFIG_CMD_IDE
  69. #define CONFIG_CMD_DHCP
  70. #undef CONFIG_CMD_ENV
  71. #undef CONFIG_CMD_FAT
  72. #undef CONFIG_CMD_FLASH
  73. #undef CONFIG_CMD_FPGA
  74. #undef CONFIG_CMD_MII
  75. #undef CONFIG_CMD_LOADS
  76. #undef CONFIG_CMD_LOADB
  77. #undef CONFIG_CMD_ELF
  78. #undef CONFIG_CMD_BDI
  79. #undef CONFIG_CMD_BEDBUG
  80. #undef CONFIG_CMD_NFS
  81. #undef CONFIG_CMD_AUTOSCRIPT
  82. /*
  83. * Miscellaneous configurable options
  84. */
  85. #define CFG_LONGHELP /* undef to save memory */
  86. #define CFG_PROMPT "GTH2 # " /* Monitor Command Prompt */
  87. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  88. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  89. #define CFG_MAXARGS 16 /* max number of command args*/
  90. #define CFG_MALLOC_LEN 128*1024
  91. #define CFG_BOOTPARAMS_LEN 128*1024
  92. #define CFG_MHZ 500
  93. #define CFG_MIPS_TIMER_FREQ (CFG_MHZ * 1000000)
  94. #define CFG_HZ 1000
  95. #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
  96. #define CFG_LOAD_ADDR 0x81000000 /* default load address */
  97. #define CFG_MEMTEST_START 0x80100000
  98. #define CFG_MEMTEST_END 0x83000000
  99. #define CONFIG_HW_WATCHDOG 1
  100. /*-----------------------------------------------------------------------
  101. * FLASH and environment organization
  102. */
  103. #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  104. #define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
  105. #define PHYS_FLASH 0xbfc00000 /* Flash Bank #1 */
  106. /* The following #defines are needed to get flash environment right */
  107. #define CFG_MONITOR_BASE TEXT_BASE
  108. #define CFG_MONITOR_LEN (192 << 10)
  109. #define CFG_INIT_SP_OFFSET 0x400000
  110. /* We boot from this flash, selected with dip switch */
  111. #define CFG_FLASH_BASE PHYS_FLASH
  112. /* timeout values are in ticks */
  113. #define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
  114. #define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
  115. #define CFG_ENV_IS_NOWHERE 1
  116. /* Address and size of Primary Environment Sector */
  117. #define CFG_ENV_ADDR 0xB0030000
  118. #define CFG_ENV_SIZE 0x10000
  119. #define CONFIG_FLASH_16BIT
  120. #define CONFIG_NR_DRAM_BANKS 2
  121. #define CONFIG_NET_MULTI
  122. #define CONFIG_MEMSIZE_IN_BYTES
  123. /*---ATA PCMCIA ------------------------------------*/
  124. #define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
  125. #define CFG_PCMCIA_MEM_ADDR 0x20000000
  126. #define CFG_PCMCIA_IO_BASE 0x28000000
  127. #define CFG_PCMCIA_ATTR_BASE 0x30000000
  128. #define CONFIG_PCMCIA_SLOT_A
  129. #define CONFIG_ATAPI 1
  130. #define CONFIG_MAC_PARTITION 1
  131. /* We run CF in "true ide" mode or a harddrive via pcmcia */
  132. #define CONFIG_IDE_PCMCIA 1
  133. /* We only support one slot for now */
  134. #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
  135. #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  136. #undef CONFIG_IDE_LED /* LED for ide not supported */
  137. #undef CONFIG_IDE_RESET /* reset for ide not supported */
  138. #define CFG_ATA_IDE0_OFFSET 0
  139. #define CFG_ATA_BASE_ADDR CFG_PCMCIA_IO_BASE
  140. /* Offset for data I/O */
  141. #define CFG_ATA_DATA_OFFSET 0
  142. /* Offset for normal register accesses */
  143. #define CFG_ATA_REG_OFFSET 0
  144. /* Offset for alternate registers */
  145. #define CFG_ATA_ALT_OFFSET 0x0200
  146. /*-----------------------------------------------------------------------
  147. * Cache Configuration
  148. */
  149. #define CFG_DCACHE_SIZE 16384
  150. #define CFG_ICACHE_SIZE 16384
  151. #define CFG_CACHELINE_SIZE 32
  152. #define GPIO_CACONFIG (1<<0)
  153. #define GPIO_DPACONFIG (1<<6)
  154. #define GPIO_ERESET (1<<11)
  155. #define GPIO_EEDQ (1<<17)
  156. #define GPIO_WDI (1<<18)
  157. #define GPIO_RJ1LY (1<<22)
  158. #define GPIO_RJ1LG (1<<23)
  159. #define GPIO_LEDCLK (1<<29)
  160. #define GPIO_LEDD (1<<30)
  161. #define GPIO_CPU_LED (1<<31)
  162. #endif /* __CONFIG_H */