Yukon8220.h 9.1 KB

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  1. /*
  2. * (C) Copyright 2004
  3. * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef __CONFIG_H
  24. #define __CONFIG_H
  25. /*
  26. * High Level Configuration Options
  27. * (easy to change)
  28. */
  29. #define CONFIG_MPC8220 1
  30. #define CONFIG_YUKON8220 1 /* ... on Yukon board */
  31. /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to
  32. determine the CPU speed. */
  33. #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */
  34. #define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 16 /* VCO multiplier can't be read from any register */
  35. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  36. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  37. /*
  38. * Serial console configuration
  39. */
  40. /* Define this for PSC console
  41. #define CONFIG_PSC_CONSOLE 1
  42. */
  43. #define CONFIG_EXTUART_CONSOLE 1
  44. #ifdef CONFIG_EXTUART_CONSOLE
  45. # define CONFIG_CONS_INDEX 1
  46. # define CFG_NS16550_SERIAL
  47. # define CFG_NS16550
  48. # define CFG_NS16550_REG_SIZE 1
  49. # define CFG_NS16550_COM1 (CFG_CPLD_BASE + 0x1008)
  50. # define CFG_NS16550_CLK 18432000
  51. #endif
  52. #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
  53. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  54. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  55. /*
  56. * Command line configuration.
  57. */
  58. #include <config_cmd_default.h>
  59. #define CONFIG_CMD_BOOTD
  60. #define CONFIG_CMD_CACHE
  61. #define CONFIG_CMD_DHCP
  62. #define CONFIG_CMD_DIAG
  63. #define CONFIG_CMD_EEPROM
  64. #define CONFIG_CMD_ELF
  65. #define CONFIG_CMD_I2C
  66. #define CONFIG_CMD_NET
  67. #define CONFIG_CMD_NFS
  68. #define CONFIG_CMD_PCI
  69. #define CONFIG_CMD_PING
  70. #define CONFIG_CMD_REGINFO
  71. #define CONFIG_CMD_SDRAM
  72. #define CONFIG_CMD_SNTP
  73. #define CONFIG_NET_MULTI
  74. #define CONFIG_MII
  75. /*
  76. * Autobooting
  77. */
  78. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  79. #define CONFIG_BOOTARGS "root=/dev/ram rw"
  80. #define CONFIG_ETHADDR 00:e0:0c:bc:e0:60
  81. #define CONFIG_HAS_ETH1
  82. #define CONFIG_ETH1ADDR 00:e0:0c:bc:e0:61
  83. #define CONFIG_IPADDR 192.162.1.2
  84. #define CONFIG_NETMASK 255.255.255.0
  85. #define CONFIG_SERVERIP 192.162.1.1
  86. #define CONFIG_GATEWAYIP 192.162.1.1
  87. #define CONFIG_HOSTNAME yukon
  88. #define CONFIG_OVERWRITE_ETHADDR_ONCE
  89. /*
  90. * I2C configuration
  91. */
  92. #define CONFIG_HARD_I2C 1
  93. #define CFG_I2C_MODULE 1
  94. #define CFG_I2C_SPEED 100000 /* 100 kHz */
  95. #define CFG_I2C_SLAVE 0x7F
  96. /*
  97. * EEPROM configuration
  98. */
  99. #define CFG_I2C_EEPROM_ADDR 0x52 /* 1011000xb */
  100. #define CFG_I2C_EEPROM_ADDR_LEN 1
  101. #define CFG_EEPROM_PAGE_WRITE_BITS 3
  102. #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
  103. /*
  104. #define CFG_ENV_IS_IN_EEPROM 1
  105. #define CFG_ENV_OFFSET 0
  106. #define CFG_ENV_SIZE 256
  107. */
  108. /* If CFG_AMD_BOOT is defined, the the system will boot from AMD.
  109. else undefined it will boot from Intel Strata flash */
  110. #define CFG_AMD_BOOT 1
  111. /*
  112. * Flexbus Chipselect configuration
  113. */
  114. #if defined (CFG_AMD_BOOT)
  115. #define CFG_CS0_BASE 0xfff0
  116. #define CFG_CS0_MASK 0x00080000 /* 512 KB */
  117. #define CFG_CS0_CTRL 0x003f0d40
  118. #define CFG_CS1_BASE 0xfe00
  119. #define CFG_CS1_MASK 0x01000000 /* 16 MB */
  120. #define CFG_CS1_CTRL 0x003f1540
  121. #else
  122. #define CFG_CS0_BASE 0xff00
  123. #define CFG_CS0_MASK 0x01000000 /* 16 MB */
  124. #define CFG_CS0_CTRL 0x003f1540
  125. #define CFG_CS1_BASE 0xfe08
  126. #define CFG_CS1_MASK 0x00080000 /* 512 KB */
  127. #define CFG_CS1_CTRL 0x003f0d40
  128. #endif
  129. #define CFG_CS2_BASE 0xf100
  130. #define CFG_CS2_MASK 0x00040000
  131. #define CFG_CS2_CTRL 0x003f1140
  132. #define CFG_CS3_BASE 0xf200
  133. #define CFG_CS3_MASK 0x00040000
  134. #define CFG_CS3_CTRL 0x003f1100
  135. #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16)
  136. #define CFG_FLASH1_BASE (CFG_CS1_BASE << 16)
  137. #if defined (CFG_AMD_BOOT)
  138. #define CFG_AMD_BASE CFG_FLASH0_BASE
  139. #define CFG_INTEL_BASE CFG_FLASH1_BASE + 0xf00000
  140. #define CFG_FLASH_BASE CFG_AMD_BASE
  141. #else
  142. #define CFG_INTEL_BASE CFG_FLASH0_BASE + 0xf00000
  143. #define CFG_AMD_BASE CFG_FLASH1_BASE
  144. #define CFG_FLASH_BASE CFG_INTEL_BASE
  145. #endif
  146. #define CFG_CPLD_BASE (CFG_CS2_BASE << 16)
  147. #define CFG_FPGA_BASE (CFG_CS3_BASE << 16)
  148. #define CFG_MAX_FLASH_BANKS 4 /* max num of memory banks */
  149. #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
  150. #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
  151. #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
  152. #define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
  153. #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
  154. #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  155. #define PHYS_AMD_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
  156. #define PHYS_INTEL_SECT_SIZE 0x00020000 /* 128 KB sectors (x2) */
  157. #define CFG_FLASH_CHECKSUM
  158. /*
  159. * Environment settings
  160. */
  161. #define CFG_ENV_IS_IN_FLASH 1
  162. #if defined (CFG_AMD_BOOT)
  163. #define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_AMD_SECT_SIZE)
  164. #define CFG_ENV_SIZE PHYS_AMD_SECT_SIZE
  165. #define CFG_ENV_SECT_SIZE PHYS_AMD_SECT_SIZE
  166. #define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_INTEL_SECT_SIZE)
  167. #define CFG_ENV1_SIZE PHYS_INTEL_SECT_SIZE
  168. #define CFG_ENV1_SECT_SIZE PHYS_INTEL_SECT_SIZE
  169. #else
  170. #define CFG_ENV_ADDR (CFG_FLASH0_BASE + CFG_CS0_MASK - PHYS_INTEL_SECT_SIZE)
  171. #define CFG_ENV_SIZE PHYS_INTEL_SECT_SIZE
  172. #define CFG_ENV_SECT_SIZE PHYS_INTEL_SECT_SIZE
  173. #define CFG_ENV1_ADDR (CFG_FLASH1_BASE + CFG_CS1_MASK - PHYS_AMD_SECT_SIZE)
  174. #define CFG_ENV1_SIZE PHYS_AMD_SECT_SIZE
  175. #define CFG_ENV1_SECT_SIZE PHYS_AMD_SECT_SIZE
  176. #endif
  177. #define CONFIG_ENV_OVERWRITE 1
  178. #if defined CFG_ENV_IS_IN_FLASH
  179. #undef CFG_ENV_IS_IN_NVRAM
  180. #undef CFG_ENV_IS_IN_EEPROM
  181. #elif defined CFG_ENV_IS_IN_NVRAM
  182. #undef CFG_ENV_IS_IN_FLASH
  183. #undef CFG_ENV_IS_IN_EEPROM
  184. #elif defined CFG_ENV_IS_IN_EEPROM
  185. #undef CFG_ENV_IS_IN_NVRAM
  186. #undef CFG_ENV_IS_IN_FLASH
  187. #endif
  188. #ifndef CFG_JFFS2_FIRST_SECTOR
  189. #define CFG_JFFS2_FIRST_SECTOR 0
  190. #endif
  191. #ifndef CFG_JFFS2_FIRST_BANK
  192. #define CFG_JFFS2_FIRST_BANK 0
  193. #endif
  194. #ifndef CFG_JFFS2_NUM_BANKS
  195. #define CFG_JFFS2_NUM_BANKS 1
  196. #endif
  197. #define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
  198. /*
  199. * Memory map
  200. */
  201. #define CFG_MBAR 0xF0000000
  202. #define CFG_SDRAM_BASE 0x00000000
  203. #define CFG_DEFAULT_MBAR 0x80000000
  204. #define CFG_SRAM_BASE (CFG_MBAR + 0x20000)
  205. #define CFG_SRAM_SIZE 0x8000
  206. /* Use SRAM until RAM will be available */
  207. #define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000)
  208. #define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */
  209. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  210. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  211. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  212. #define CFG_MONITOR_BASE TEXT_BASE
  213. #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
  214. # define CFG_RAMBOOT 1
  215. #endif
  216. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  217. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  218. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  219. /* SDRAM configuration */
  220. #define CFG_SDRAM_TOTAL_BANKS 2
  221. #define CFG_SDRAM_SPD_I2C_ADDR 0x51 /* 7bit */
  222. #define CFG_SDRAM_SPD_SIZE 0x40
  223. #define CFG_SDRAM_CAS_LATENCY 4 /* (CL=2)x2 */
  224. /* SDRAM drive strength register */
  225. #define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_LOW << SDRAMDS_SBE_SHIFT) | \
  226. (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \
  227. (DRIVE_STRENGTH_LOW << SDRAMDS_SBA_SHIFT) | \
  228. (DRIVE_STRENGTH_OFF << SDRAMDS_SBS_SHIFT) | \
  229. (DRIVE_STRENGTH_LOW << SDRAMDS_SBD_SHIFT))
  230. /*
  231. * Ethernet configuration
  232. */
  233. #define CONFIG_MPC8220_FEC 1
  234. #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
  235. #define CONFIG_PHY_ADDR 0x18
  236. /*
  237. * Miscellaneous configurable options
  238. */
  239. #define CFG_LONGHELP /* undef to save memory */
  240. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  241. #if defined(CONFIG_CMD_KGDB)
  242. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  243. #else
  244. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  245. #endif
  246. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  247. #define CFG_MAXARGS 16 /* max number of command args */
  248. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  249. #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
  250. #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
  251. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  252. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  253. #define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */
  254. #if defined(CONFIG_CMD_KGDB)
  255. # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  256. #endif
  257. /*
  258. * Various low-level settings
  259. */
  260. #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
  261. #define CFG_HID0_FINAL HID0_ICE
  262. #endif /* __CONFIG_H */