exbitgen.c 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127
  1. #include <asm/types.h>
  2. #include <asm/u-boot.h>
  3. #include <asm/processor.h>
  4. #include <common.h>
  5. #include "exbitgen.h"
  6. void sdram_init(void);
  7. /* ************************************************************************ */
  8. int board_early_init_f (void)
  9. /* ------------------------------------------------------------------------ --
  10. * Purpose :
  11. * Remarks :
  12. * Restrictions:
  13. * See also :
  14. * Example :
  15. * ************************************************************************ */
  16. {
  17. unsigned long i;
  18. /*-------------------------------------------------------------------------+
  19. | Interrupt controller setup for the Walnut board.
  20. | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
  21. | IRQ 16 405GP internally generated; active low; level sensitive
  22. | IRQ 17-24 RESERVED
  23. | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
  24. | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
  25. | IRQ 27 (EXT IRQ 2) Not Used
  26. | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  27. | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  28. | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  29. | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  30. | Note for Walnut board:
  31. | An interrupt taken for the FPGA (IRQ 25) indicates that either
  32. | the Mouse, Keyboard, IRDA, or External Expansion caused the
  33. | interrupt. The FPGA must be read to determine which device
  34. | caused the interrupt. The default setting of the FPGA clears
  35. |
  36. +-------------------------------------------------------------------------*/
  37. mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  38. mtdcr (uicer, 0x00000000); /* disable all ints */
  39. mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
  40. mtdcr (uicpr, 0xFFFFFF90); /* set int polarities */
  41. mtdcr (uictr, 0x10000000); /* set int trigger levels */
  42. mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
  43. mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  44. /* Perform reset of PHY connected to PPC via register in CPLD */
  45. out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */
  46. for (i = 0; i < 10000000; i++) {
  47. ;
  48. }
  49. out8 (PHY_CTRL_ADDR, 0x2f); /* deactivate nRESET */
  50. return 0;
  51. }
  52. /* ************************************************************************ */
  53. int checkboard (void)
  54. /* ------------------------------------------------------------------------ --
  55. * Purpose :
  56. * Remarks :
  57. * Restrictions:
  58. * See also :
  59. * Example :
  60. * ************************************************************************ */
  61. {
  62. printf ("Exbit H/W id: %d\n", in8 (HW_ID_ADDR));
  63. return (0);
  64. }
  65. /* ************************************************************************ */
  66. phys_size_t initdram (int board_type)
  67. /* ------------------------------------------------------------------------ --
  68. * Purpose : Determines size of mounted DRAM.
  69. * Remarks : Size is determined by reading SDRAM configuration registers as
  70. * set up by sdram_init.
  71. * Restrictions:
  72. * See also :
  73. * Example :
  74. * ************************************************************************ */
  75. {
  76. ulong tot_size;
  77. ulong bank_size;
  78. ulong tmp;
  79. /*
  80. * ToDo: Move the asm init routine sdram_init() to this C file,
  81. * or even better use some common ppc4xx code available
  82. * in cpu/ppc4xx
  83. */
  84. sdram_init();
  85. tot_size = 0;
  86. mtdcr (memcfga, mem_mb0cf);
  87. tmp = mfdcr (memcfgd);
  88. if (tmp & 0x00000001) {
  89. bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  90. tot_size += bank_size;
  91. }
  92. mtdcr (memcfga, mem_mb1cf);
  93. tmp = mfdcr (memcfgd);
  94. if (tmp & 0x00000001) {
  95. bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  96. tot_size += bank_size;
  97. }
  98. mtdcr (memcfga, mem_mb2cf);
  99. tmp = mfdcr (memcfgd);
  100. if (tmp & 0x00000001) {
  101. bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  102. tot_size += bank_size;
  103. }
  104. mtdcr (memcfga, mem_mb3cf);
  105. tmp = mfdcr (memcfgd);
  106. if (tmp & 0x00000001) {
  107. bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  108. tot_size += bank_size;
  109. }
  110. return tot_size;
  111. }