afeb9260.c 4.9 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stelian Pop <stelian.pop@leadtechdesign.com>
  4. * Lead Tech Design <www.leadtechdesign.com>
  5. * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <common.h>
  26. #include <asm/arch/at91sam9260.h>
  27. #include <asm/arch/at91sam9260_matrix.h>
  28. #include <asm/arch/at91sam9_smc.h>
  29. #include <asm/arch/at91_common.h>
  30. #include <asm/arch/at91_pmc.h>
  31. #include <asm/arch/at91_rstc.h>
  32. #include <asm/arch/gpio.h>
  33. #include <asm/arch/io.h>
  34. #include <asm/arch/hardware.h>
  35. #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  36. #include <netdev.h>
  37. #include <net.h>
  38. #endif
  39. DECLARE_GLOBAL_DATA_PTR;
  40. /* ------------------------------------------------------------------------- */
  41. /*
  42. * Miscelaneous platform dependent initialisations
  43. */
  44. static void afeb9260_nand_hw_init(void)
  45. {
  46. unsigned long csa;
  47. /* Enable CS3 */
  48. csa = at91_sys_read(AT91_MATRIX_EBICSA);
  49. at91_sys_write(AT91_MATRIX_EBICSA,
  50. csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
  51. /* Configure SMC CS3 for NAND/SmartMedia */
  52. at91_sys_write(AT91_SMC_SETUP(3),
  53. AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
  54. AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
  55. at91_sys_write(AT91_SMC_PULSE(3),
  56. AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  57. AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  58. at91_sys_write(AT91_SMC_CYCLE(3),
  59. AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  60. at91_sys_write(AT91_SMC_MODE(3),
  61. AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  62. AT91_SMC_EXNWMODE_DISABLE |
  63. AT91_SMC_DBW_8 |
  64. AT91_SMC_TDF_(2));
  65. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
  66. /* Configure RDY/BSY */
  67. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  68. /* Enable NandFlash */
  69. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  70. }
  71. #ifdef CONFIG_MACB
  72. static void afeb9260_macb_hw_init(void)
  73. {
  74. unsigned long rstc;
  75. /* Enable clock */
  76. at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
  77. /*
  78. * Disable pull-up on:
  79. * RXDV (PA17) => PHY normal mode (not Test mode)
  80. * ERX0 (PA14) => PHY ADDR0
  81. * ERX1 (PA15) => PHY ADDR1
  82. * ERX2 (PA25) => PHY ADDR2
  83. * ERX3 (PA26) => PHY ADDR3
  84. * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
  85. *
  86. * PHY has internal pull-down
  87. */
  88. writel(pin_to_mask(AT91_PIN_PA14) |
  89. pin_to_mask(AT91_PIN_PA15) |
  90. pin_to_mask(AT91_PIN_PA17) |
  91. pin_to_mask(AT91_PIN_PA25) |
  92. pin_to_mask(AT91_PIN_PA26) |
  93. pin_to_mask(AT91_PIN_PA28),
  94. pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
  95. rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
  96. /* Need to reset PHY -> 500ms reset */
  97. at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
  98. AT91_RSTC_ERSTL | (0x0D << 8) |
  99. AT91_RSTC_URSTEN);
  100. at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
  101. /* Wait for end hardware reset */
  102. while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
  103. /* Restore NRST value */
  104. at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
  105. (rstc) |
  106. AT91_RSTC_URSTEN);
  107. /* Re-enable pull-up */
  108. writel(pin_to_mask(AT91_PIN_PA14) |
  109. pin_to_mask(AT91_PIN_PA15) |
  110. pin_to_mask(AT91_PIN_PA17) |
  111. pin_to_mask(AT91_PIN_PA25) |
  112. pin_to_mask(AT91_PIN_PA26) |
  113. pin_to_mask(AT91_PIN_PA28),
  114. pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
  115. at91_macb_hw_init();
  116. }
  117. #endif
  118. int board_init(void)
  119. {
  120. /* Enable Ctrlc */
  121. console_init_f();
  122. /* arch number of AT91SAM9260EK-Board */
  123. gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
  124. /* adress of boot parameters */
  125. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  126. at91_serial_hw_init();
  127. #ifdef CONFIG_CMD_NAND
  128. afeb9260_nand_hw_init();
  129. #endif
  130. at91_spi0_hw_init((1 << 0) || (1 << 1));
  131. #ifdef CONFIG_MACB
  132. afeb9260_macb_hw_init();
  133. #endif
  134. return 0;
  135. }
  136. int dram_init(void)
  137. {
  138. gd->bd->bi_dram[0].start = PHYS_SDRAM;
  139. gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
  140. return 0;
  141. }
  142. #ifdef CONFIG_RESET_PHY_R
  143. void reset_phy(void)
  144. {
  145. #ifdef CONFIG_MACB
  146. /*
  147. * Initialize ethernet HW addr prior to starting Linux,
  148. * needed for nfsroot
  149. */
  150. eth_init(gd->bd);
  151. #endif
  152. }
  153. #endif
  154. int board_eth_init(bd_t *bis)
  155. {
  156. int rc = 0;
  157. #ifdef CONFIG_MACB
  158. rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x01);
  159. #endif
  160. return rc;
  161. }