usb_ohci.c 42 KB

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  1. /*
  2. * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
  3. *
  4. * (C) Copyright 2003
  5. * Gary Jennejohn, DENX Software Engineering <gj@denx.de>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. *
  25. * Note: Part of this code has been derived from linux
  26. *
  27. */
  28. /*
  29. * IMPORTANT NOTES
  30. * 1 - you MUST define LITTLEENDIAN in the configuration file for the
  31. * board or this driver will NOT work!
  32. * 2 - this driver is intended for use with USB Mass Storage Devices
  33. * (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
  34. */
  35. #include <common.h>
  36. /* #include <pci.h> no PCI on the S3C2400 */
  37. #ifdef CONFIG_USB_OHCI
  38. #include <s3c2400.h>
  39. #include <malloc.h>
  40. #include <usb.h>
  41. #include "usb_ohci.h"
  42. #define OHCI_USE_NPS /* force NoPowerSwitching mode */
  43. #undef OHCI_VERBOSE_DEBUG /* not always helpful */
  44. /* For initializing controller (mask in an HCFS mode too) */
  45. #define OHCI_CONTROL_INIT \
  46. (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  47. #define OHCI_UNLINK_TIMEOUT (CFG_HZ / 10)
  48. #define readl(a) (*((vu_long *)(a)))
  49. #define writel(a, b) (*((vu_long *)(b)) = ((vu_long)a))
  50. #define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
  51. #undef DEBUG
  52. #ifdef DEBUG
  53. #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  54. #else
  55. #define dbg(format, arg...) do {} while(0)
  56. #endif /* DEBUG */
  57. #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  58. #undef SHOW_INFO
  59. #ifdef SHOW_INFO
  60. #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  61. #else
  62. #define info(format, arg...) do {} while(0)
  63. #endif
  64. #define m16_swap(x) swap_16(x)
  65. #define m32_swap(x) swap_32(x)
  66. /* global ohci_t */
  67. static ohci_t gohci;
  68. /* this must be aligned to a 256 byte boundary */
  69. struct ohci_hcca ghcca[1];
  70. /* a pointer to the aligned storage */
  71. struct ohci_hcca *phcca;
  72. /* this allocates EDs for all possible endpoints */
  73. struct ohci_device ohci_dev;
  74. /* urb_priv */
  75. urb_priv_t urb_priv;
  76. /*-------------------------------------------------------------------------*/
  77. /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  78. * The erratum (#4) description is incorrect. AMD's workaround waits
  79. * till some bits (mostly reserved) are clear; ok for all revs.
  80. */
  81. #define OHCI_QUIRK_AMD756 0xabcd
  82. #define read_roothub(hc, register, mask) ({ \
  83. u32 temp = readl (&hc->regs->roothub.register); \
  84. if (hc->flags & OHCI_QUIRK_AMD756) \
  85. while (temp & mask) \
  86. temp = readl (&hc->regs->roothub.register); \
  87. temp; })
  88. static u32 roothub_a (struct ohci *hc)
  89. { return read_roothub (hc, a, 0xfc0fe000); }
  90. static inline u32 roothub_b (struct ohci *hc)
  91. { return readl (&hc->regs->roothub.b); }
  92. static inline u32 roothub_status (struct ohci *hc)
  93. { return readl (&hc->regs->roothub.status); }
  94. static u32 roothub_portstatus (struct ohci *hc, int i)
  95. { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
  96. /* forward declaration */
  97. static int hc_interrupt (void);
  98. static void
  99. td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
  100. int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
  101. /*-------------------------------------------------------------------------*
  102. * URB support functions
  103. *-------------------------------------------------------------------------*/
  104. /* free HCD-private data associated with this URB */
  105. static void urb_free_priv (urb_priv_t * urb)
  106. {
  107. int i;
  108. int last;
  109. struct td * td;
  110. last = urb->length - 1;
  111. if (last >= 0) {
  112. for (i = 0; i <= last; i++) {
  113. td = urb->td[i];
  114. if (td) {
  115. td->usb_dev = NULL;
  116. urb->td[i] = NULL;
  117. }
  118. }
  119. }
  120. }
  121. /*-------------------------------------------------------------------------*/
  122. #ifdef DEBUG
  123. static int sohci_get_current_frame_number (struct usb_device * dev);
  124. /* debug| print the main components of an URB
  125. * small: 0) header + data packets 1) just header */
  126. static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
  127. int transfer_len, struct devrequest * setup, char * str, int small)
  128. {
  129. urb_priv_t * purb = &urb_priv;
  130. dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
  131. str,
  132. sohci_get_current_frame_number (dev),
  133. usb_pipedevice (pipe),
  134. usb_pipeendpoint (pipe),
  135. usb_pipeout (pipe)? 'O': 'I',
  136. usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
  137. (usb_pipecontrol (pipe)? "CTRL": "BULK"),
  138. purb->actual_length,
  139. transfer_len, dev->status);
  140. #ifdef OHCI_VERBOSE_DEBUG
  141. if (!small) {
  142. int i, len;
  143. if (usb_pipecontrol (pipe)) {
  144. printf (__FILE__ ": cmd(8):");
  145. for (i = 0; i < 8 ; i++)
  146. printf (" %02x", ((__u8 *) setup) [i]);
  147. printf ("\n");
  148. }
  149. if (transfer_len > 0 && buffer) {
  150. printf (__FILE__ ": data(%d/%d):",
  151. purb->actual_length,
  152. transfer_len);
  153. len = usb_pipeout (pipe)?
  154. transfer_len: purb->actual_length;
  155. for (i = 0; i < 16 && i < len; i++)
  156. printf (" %02x", ((__u8 *) buffer) [i]);
  157. printf ("%s\n", i < len? "...": "");
  158. }
  159. }
  160. #endif
  161. }
  162. /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
  163. void ep_print_int_eds (ohci_t *ohci, char * str) {
  164. int i, j;
  165. __u32 * ed_p;
  166. for (i= 0; i < 32; i++) {
  167. j = 5;
  168. ed_p = &(ohci->hcca->int_table [i]);
  169. if (*ed_p == 0)
  170. continue;
  171. printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
  172. while (*ed_p != 0 && j--) {
  173. ed_t *ed = (ed_t *)m32_swap(ed_p);
  174. printf (" ed: %4x;", ed->hwINFO);
  175. ed_p = &ed->hwNextED;
  176. }
  177. printf ("\n");
  178. }
  179. }
  180. static void ohci_dump_intr_mask (char *label, __u32 mask)
  181. {
  182. dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
  183. label,
  184. mask,
  185. (mask & OHCI_INTR_MIE) ? " MIE" : "",
  186. (mask & OHCI_INTR_OC) ? " OC" : "",
  187. (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
  188. (mask & OHCI_INTR_FNO) ? " FNO" : "",
  189. (mask & OHCI_INTR_UE) ? " UE" : "",
  190. (mask & OHCI_INTR_RD) ? " RD" : "",
  191. (mask & OHCI_INTR_SF) ? " SF" : "",
  192. (mask & OHCI_INTR_WDH) ? " WDH" : "",
  193. (mask & OHCI_INTR_SO) ? " SO" : ""
  194. );
  195. }
  196. static void maybe_print_eds (char *label, __u32 value)
  197. {
  198. ed_t *edp = (ed_t *)value;
  199. if (value) {
  200. dbg ("%s %08x", label, value);
  201. dbg ("%08x", edp->hwINFO);
  202. dbg ("%08x", edp->hwTailP);
  203. dbg ("%08x", edp->hwHeadP);
  204. dbg ("%08x", edp->hwNextED);
  205. }
  206. }
  207. static char * hcfs2string (int state)
  208. {
  209. switch (state) {
  210. case OHCI_USB_RESET: return "reset";
  211. case OHCI_USB_RESUME: return "resume";
  212. case OHCI_USB_OPER: return "operational";
  213. case OHCI_USB_SUSPEND: return "suspend";
  214. }
  215. return "?";
  216. }
  217. /* dump control and status registers */
  218. static void ohci_dump_status (ohci_t *controller)
  219. {
  220. struct ohci_regs *regs = controller->regs;
  221. __u32 temp;
  222. temp = readl (&regs->revision) & 0xff;
  223. if (temp != 0x10)
  224. dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
  225. temp = readl (&regs->control);
  226. dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
  227. (temp & OHCI_CTRL_RWE) ? " RWE" : "",
  228. (temp & OHCI_CTRL_RWC) ? " RWC" : "",
  229. (temp & OHCI_CTRL_IR) ? " IR" : "",
  230. hcfs2string (temp & OHCI_CTRL_HCFS),
  231. (temp & OHCI_CTRL_BLE) ? " BLE" : "",
  232. (temp & OHCI_CTRL_CLE) ? " CLE" : "",
  233. (temp & OHCI_CTRL_IE) ? " IE" : "",
  234. (temp & OHCI_CTRL_PLE) ? " PLE" : "",
  235. temp & OHCI_CTRL_CBSR
  236. );
  237. temp = readl (&regs->cmdstatus);
  238. dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
  239. (temp & OHCI_SOC) >> 16,
  240. (temp & OHCI_OCR) ? " OCR" : "",
  241. (temp & OHCI_BLF) ? " BLF" : "",
  242. (temp & OHCI_CLF) ? " CLF" : "",
  243. (temp & OHCI_HCR) ? " HCR" : ""
  244. );
  245. ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
  246. ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
  247. maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
  248. maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
  249. maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
  250. maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
  251. maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
  252. maybe_print_eds ("donehead", readl (&regs->donehead));
  253. }
  254. static void ohci_dump_roothub (ohci_t *controller, int verbose)
  255. {
  256. __u32 temp, ndp, i;
  257. temp = roothub_a (controller);
  258. ndp = (temp & RH_A_NDP);
  259. if (verbose) {
  260. dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
  261. ((temp & RH_A_POTPGT) >> 24) & 0xff,
  262. (temp & RH_A_NOCP) ? " NOCP" : "",
  263. (temp & RH_A_OCPM) ? " OCPM" : "",
  264. (temp & RH_A_DT) ? " DT" : "",
  265. (temp & RH_A_NPS) ? " NPS" : "",
  266. (temp & RH_A_PSM) ? " PSM" : "",
  267. ndp
  268. );
  269. temp = roothub_b (controller);
  270. dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
  271. temp,
  272. (temp & RH_B_PPCM) >> 16,
  273. (temp & RH_B_DR)
  274. );
  275. temp = roothub_status (controller);
  276. dbg ("roothub.status: %08x%s%s%s%s%s%s",
  277. temp,
  278. (temp & RH_HS_CRWE) ? " CRWE" : "",
  279. (temp & RH_HS_OCIC) ? " OCIC" : "",
  280. (temp & RH_HS_LPSC) ? " LPSC" : "",
  281. (temp & RH_HS_DRWE) ? " DRWE" : "",
  282. (temp & RH_HS_OCI) ? " OCI" : "",
  283. (temp & RH_HS_LPS) ? " LPS" : ""
  284. );
  285. }
  286. for (i = 0; i < ndp; i++) {
  287. temp = roothub_portstatus (controller, i);
  288. dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
  289. i,
  290. temp,
  291. (temp & RH_PS_PRSC) ? " PRSC" : "",
  292. (temp & RH_PS_OCIC) ? " OCIC" : "",
  293. (temp & RH_PS_PSSC) ? " PSSC" : "",
  294. (temp & RH_PS_PESC) ? " PESC" : "",
  295. (temp & RH_PS_CSC) ? " CSC" : "",
  296. (temp & RH_PS_LSDA) ? " LSDA" : "",
  297. (temp & RH_PS_PPS) ? " PPS" : "",
  298. (temp & RH_PS_PRS) ? " PRS" : "",
  299. (temp & RH_PS_POCI) ? " POCI" : "",
  300. (temp & RH_PS_PSS) ? " PSS" : "",
  301. (temp & RH_PS_PES) ? " PES" : "",
  302. (temp & RH_PS_CCS) ? " CCS" : ""
  303. );
  304. }
  305. }
  306. static void ohci_dump (ohci_t *controller, int verbose)
  307. {
  308. dbg ("OHCI controller usb-%s state", controller->slot_name);
  309. /* dumps some of the state we know about */
  310. ohci_dump_status (controller);
  311. if (verbose)
  312. ep_print_int_eds (controller, "hcca");
  313. dbg ("hcca frame #%04x", controller->hcca->frame_no);
  314. ohci_dump_roothub (controller, 1);
  315. }
  316. #endif /* DEBUG */
  317. /*-------------------------------------------------------------------------*
  318. * Interface functions (URB)
  319. *-------------------------------------------------------------------------*/
  320. /* get a transfer request */
  321. int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
  322. int transfer_len, struct devrequest *setup, int interval)
  323. {
  324. ohci_t *ohci;
  325. ed_t * ed;
  326. urb_priv_t *purb_priv;
  327. int i, size = 0;
  328. ohci = &gohci;
  329. /* when controller's hung, permit only roothub cleanup attempts
  330. * such as powering down ports */
  331. if (ohci->disabled) {
  332. err("sohci_submit_job: EPIPE");
  333. return -1;
  334. }
  335. /* every endpoint has a ed, locate and fill it */
  336. if (!(ed = ep_add_ed (dev, pipe))) {
  337. err("sohci_submit_job: ENOMEM");
  338. return -1;
  339. }
  340. /* for the private part of the URB we need the number of TDs (size) */
  341. switch (usb_pipetype (pipe)) {
  342. case PIPE_BULK: /* one TD for every 4096 Byte */
  343. size = (transfer_len - 1) / 4096 + 1;
  344. break;
  345. case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
  346. size = (transfer_len == 0)? 2:
  347. (transfer_len - 1) / 4096 + 3;
  348. break;
  349. }
  350. if (size >= (N_URB_TD - 1)) {
  351. err("need %d TDs, only have %d", size, N_URB_TD);
  352. return -1;
  353. }
  354. purb_priv = &urb_priv;
  355. purb_priv->pipe = pipe;
  356. /* fill the private part of the URB */
  357. purb_priv->length = size;
  358. purb_priv->ed = ed;
  359. purb_priv->actual_length = 0;
  360. /* allocate the TDs */
  361. /* note that td[0] was allocated in ep_add_ed */
  362. for (i = 0; i < size; i++) {
  363. purb_priv->td[i] = td_alloc (dev);
  364. if (!purb_priv->td[i]) {
  365. purb_priv->length = i;
  366. urb_free_priv (purb_priv);
  367. err("sohci_submit_job: ENOMEM");
  368. return -1;
  369. }
  370. }
  371. if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
  372. urb_free_priv (purb_priv);
  373. err("sohci_submit_job: EINVAL");
  374. return -1;
  375. }
  376. /* link the ed into a chain if is not already */
  377. if (ed->state != ED_OPER)
  378. ep_link (ohci, ed);
  379. /* fill the TDs and link it to the ed */
  380. td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
  381. return 0;
  382. }
  383. /*-------------------------------------------------------------------------*/
  384. #ifdef DEBUG
  385. /* tell us the current USB frame number */
  386. static int sohci_get_current_frame_number (struct usb_device *usb_dev)
  387. {
  388. ohci_t *ohci = &gohci;
  389. return m16_swap (ohci->hcca->frame_no);
  390. }
  391. #endif
  392. /*-------------------------------------------------------------------------*
  393. * ED handling functions
  394. *-------------------------------------------------------------------------*/
  395. /* link an ed into one of the HC chains */
  396. static int ep_link (ohci_t *ohci, ed_t *edi)
  397. {
  398. volatile ed_t *ed = edi;
  399. ed->state = ED_OPER;
  400. switch (ed->type) {
  401. case PIPE_CONTROL:
  402. ed->hwNextED = 0;
  403. if (ohci->ed_controltail == NULL) {
  404. writel (ed, &ohci->regs->ed_controlhead);
  405. } else {
  406. ohci->ed_controltail->hwNextED = m32_swap (ed);
  407. }
  408. ed->ed_prev = ohci->ed_controltail;
  409. if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
  410. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  411. ohci->hc_control |= OHCI_CTRL_CLE;
  412. writel (ohci->hc_control, &ohci->regs->control);
  413. }
  414. ohci->ed_controltail = edi;
  415. break;
  416. case PIPE_BULK:
  417. ed->hwNextED = 0;
  418. if (ohci->ed_bulktail == NULL) {
  419. writel (ed, &ohci->regs->ed_bulkhead);
  420. } else {
  421. ohci->ed_bulktail->hwNextED = m32_swap (ed);
  422. }
  423. ed->ed_prev = ohci->ed_bulktail;
  424. if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
  425. !ohci->ed_rm_list[1] && !ohci->sleeping) {
  426. ohci->hc_control |= OHCI_CTRL_BLE;
  427. writel (ohci->hc_control, &ohci->regs->control);
  428. }
  429. ohci->ed_bulktail = edi;
  430. break;
  431. }
  432. return 0;
  433. }
  434. /*-------------------------------------------------------------------------*/
  435. /* unlink an ed from one of the HC chains.
  436. * just the link to the ed is unlinked.
  437. * the link from the ed still points to another operational ed or 0
  438. * so the HC can eventually finish the processing of the unlinked ed */
  439. static int ep_unlink (ohci_t *ohci, ed_t *ed)
  440. {
  441. ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
  442. switch (ed->type) {
  443. case PIPE_CONTROL:
  444. if (ed->ed_prev == NULL) {
  445. if (!ed->hwNextED) {
  446. ohci->hc_control &= ~OHCI_CTRL_CLE;
  447. writel (ohci->hc_control, &ohci->regs->control);
  448. }
  449. writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
  450. } else {
  451. ed->ed_prev->hwNextED = ed->hwNextED;
  452. }
  453. if (ohci->ed_controltail == ed) {
  454. ohci->ed_controltail = ed->ed_prev;
  455. } else {
  456. ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  457. }
  458. break;
  459. case PIPE_BULK:
  460. if (ed->ed_prev == NULL) {
  461. if (!ed->hwNextED) {
  462. ohci->hc_control &= ~OHCI_CTRL_BLE;
  463. writel (ohci->hc_control, &ohci->regs->control);
  464. }
  465. writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
  466. } else {
  467. ed->ed_prev->hwNextED = ed->hwNextED;
  468. }
  469. if (ohci->ed_bulktail == ed) {
  470. ohci->ed_bulktail = ed->ed_prev;
  471. } else {
  472. ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
  473. }
  474. break;
  475. }
  476. ed->state = ED_UNLINK;
  477. return 0;
  478. }
  479. /*-------------------------------------------------------------------------*/
  480. /* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
  481. * but the USB stack is a little bit stateless so we do it at every transaction
  482. * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
  483. * in all other cases the state is left unchanged
  484. * the ed info fields are setted anyway even though most of them should not change */
  485. static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
  486. {
  487. td_t *td;
  488. ed_t *ed_ret;
  489. volatile ed_t *ed;
  490. ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
  491. (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
  492. if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
  493. err("ep_add_ed: pending delete");
  494. /* pending delete request */
  495. return NULL;
  496. }
  497. if (ed->state == ED_NEW) {
  498. ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
  499. /* dummy td; end of td list for ed */
  500. td = td_alloc (usb_dev);
  501. ed->hwTailP = m32_swap (td);
  502. ed->hwHeadP = ed->hwTailP;
  503. ed->state = ED_UNLINK;
  504. ed->type = usb_pipetype (pipe);
  505. ohci_dev.ed_cnt++;
  506. }
  507. ed->hwINFO = m32_swap (usb_pipedevice (pipe)
  508. | usb_pipeendpoint (pipe) << 7
  509. | (usb_pipeisoc (pipe)? 0x8000: 0)
  510. | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
  511. | usb_pipeslow (pipe) << 13
  512. | usb_maxpacket (usb_dev, pipe) << 16);
  513. return ed_ret;
  514. }
  515. /*-------------------------------------------------------------------------*
  516. * TD handling functions
  517. *-------------------------------------------------------------------------*/
  518. /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
  519. static void td_fill (ohci_t *ohci, unsigned int info,
  520. void *data, int len,
  521. struct usb_device *dev, int index, urb_priv_t *urb_priv)
  522. {
  523. volatile td_t *td, *td_pt;
  524. #ifdef OHCI_FILL_TRACE
  525. int i;
  526. #endif
  527. if (index > urb_priv->length) {
  528. err("index > length");
  529. return;
  530. }
  531. /* use this td as the next dummy */
  532. td_pt = urb_priv->td [index];
  533. td_pt->hwNextTD = 0;
  534. /* fill the old dummy TD */
  535. td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
  536. td->ed = urb_priv->ed;
  537. td->next_dl_td = NULL;
  538. td->index = index;
  539. td->data = (__u32)data;
  540. #ifdef OHCI_FILL_TRACE
  541. if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
  542. for (i = 0; i < len; i++)
  543. printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
  544. printf("\n");
  545. }
  546. #endif
  547. if (!len)
  548. data = 0;
  549. td->hwINFO = m32_swap (info);
  550. td->hwCBP = m32_swap (data);
  551. if (data)
  552. td->hwBE = m32_swap (data + len - 1);
  553. else
  554. td->hwBE = 0;
  555. td->hwNextTD = m32_swap (td_pt);
  556. td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
  557. /* append to queue */
  558. td->ed->hwTailP = td->hwNextTD;
  559. }
  560. /*-------------------------------------------------------------------------*/
  561. /* prepare all TDs of a transfer */
  562. static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
  563. int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
  564. {
  565. ohci_t *ohci = &gohci;
  566. int data_len = transfer_len;
  567. void *data;
  568. int cnt = 0;
  569. __u32 info = 0;
  570. unsigned int toggle = 0;
  571. /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
  572. if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
  573. toggle = TD_T_TOGGLE;
  574. } else {
  575. toggle = TD_T_DATA0;
  576. usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
  577. }
  578. urb->td_cnt = 0;
  579. if (data_len)
  580. data = buffer;
  581. else
  582. data = 0;
  583. switch (usb_pipetype (pipe)) {
  584. case PIPE_BULK:
  585. info = usb_pipeout (pipe)?
  586. TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
  587. while(data_len > 4096) {
  588. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
  589. data += 4096; data_len -= 4096; cnt++;
  590. }
  591. info = usb_pipeout (pipe)?
  592. TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
  593. td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
  594. cnt++;
  595. if (!ohci->sleeping)
  596. writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
  597. break;
  598. case PIPE_CONTROL:
  599. info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
  600. td_fill (ohci, info, setup, 8, dev, cnt++, urb);
  601. if (data_len > 0) {
  602. info = usb_pipeout (pipe)?
  603. TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
  604. /* NOTE: mishandles transfers >8K, some >4K */
  605. td_fill (ohci, info, data, data_len, dev, cnt++, urb);
  606. }
  607. info = usb_pipeout (pipe)?
  608. TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
  609. td_fill (ohci, info, data, 0, dev, cnt++, urb);
  610. if (!ohci->sleeping)
  611. writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
  612. break;
  613. }
  614. if (urb->length != cnt)
  615. dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
  616. }
  617. /*-------------------------------------------------------------------------*
  618. * Done List handling functions
  619. *-------------------------------------------------------------------------*/
  620. /* calculate the transfer length and update the urb */
  621. static void dl_transfer_length(td_t * td)
  622. {
  623. __u32 tdINFO, tdBE, tdCBP;
  624. urb_priv_t *lurb_priv = &urb_priv;
  625. tdINFO = m32_swap (td->hwINFO);
  626. tdBE = m32_swap (td->hwBE);
  627. tdCBP = m32_swap (td->hwCBP);
  628. if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
  629. ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
  630. if (tdBE != 0) {
  631. if (td->hwCBP == 0)
  632. lurb_priv->actual_length += tdBE - td->data + 1;
  633. else
  634. lurb_priv->actual_length += tdCBP - td->data;
  635. }
  636. }
  637. }
  638. /*-------------------------------------------------------------------------*/
  639. /* replies to the request have to be on a FIFO basis so
  640. * we reverse the reversed done-list */
  641. static td_t * dl_reverse_done_list (ohci_t *ohci)
  642. {
  643. __u32 td_list_hc;
  644. td_t *td_rev = NULL;
  645. td_t *td_list = NULL;
  646. urb_priv_t *lurb_priv = NULL;
  647. td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
  648. ohci->hcca->done_head = 0;
  649. while (td_list_hc) {
  650. td_list = (td_t *)td_list_hc;
  651. if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
  652. lurb_priv = &urb_priv;
  653. dbg(" USB-error/status: %x : %p",
  654. TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
  655. if (td_list->ed->hwHeadP & m32_swap (0x1)) {
  656. if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
  657. td_list->ed->hwHeadP =
  658. (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
  659. (td_list->ed->hwHeadP & m32_swap (0x2));
  660. lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
  661. } else
  662. td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
  663. }
  664. }
  665. td_list->next_dl_td = td_rev;
  666. td_rev = td_list;
  667. td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
  668. }
  669. return td_list;
  670. }
  671. /*-------------------------------------------------------------------------*/
  672. /* td done list */
  673. static int dl_done_list (ohci_t *ohci, td_t *td_list)
  674. {
  675. td_t *td_list_next = NULL;
  676. ed_t *ed;
  677. int cc = 0;
  678. int stat = 0;
  679. /* urb_t *urb; */
  680. urb_priv_t *lurb_priv;
  681. __u32 tdINFO, edHeadP, edTailP;
  682. while (td_list) {
  683. td_list_next = td_list->next_dl_td;
  684. lurb_priv = &urb_priv;
  685. tdINFO = m32_swap (td_list->hwINFO);
  686. ed = td_list->ed;
  687. dl_transfer_length(td_list);
  688. /* error code of transfer */
  689. cc = TD_CC_GET (tdINFO);
  690. if (cc != 0) {
  691. dbg("ConditionCode %#x", cc);
  692. stat = cc_to_error[cc];
  693. }
  694. if (ed->state != ED_NEW) {
  695. edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
  696. edTailP = m32_swap (ed->hwTailP);
  697. /* unlink eds if they are not busy */
  698. if ((edHeadP == edTailP) && (ed->state == ED_OPER))
  699. ep_unlink (ohci, ed);
  700. }
  701. td_list = td_list_next;
  702. }
  703. return stat;
  704. }
  705. /*-------------------------------------------------------------------------*
  706. * Virtual Root Hub
  707. *-------------------------------------------------------------------------*/
  708. /* Device descriptor */
  709. static __u8 root_hub_dev_des[] =
  710. {
  711. 0x12, /* __u8 bLength; */
  712. 0x01, /* __u8 bDescriptorType; Device */
  713. 0x10, /* __u16 bcdUSB; v1.1 */
  714. 0x01,
  715. 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
  716. 0x00, /* __u8 bDeviceSubClass; */
  717. 0x00, /* __u8 bDeviceProtocol; */
  718. 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
  719. 0x00, /* __u16 idVendor; */
  720. 0x00,
  721. 0x00, /* __u16 idProduct; */
  722. 0x00,
  723. 0x00, /* __u16 bcdDevice; */
  724. 0x00,
  725. 0x00, /* __u8 iManufacturer; */
  726. 0x01, /* __u8 iProduct; */
  727. 0x00, /* __u8 iSerialNumber; */
  728. 0x01 /* __u8 bNumConfigurations; */
  729. };
  730. /* Configuration descriptor */
  731. static __u8 root_hub_config_des[] =
  732. {
  733. 0x09, /* __u8 bLength; */
  734. 0x02, /* __u8 bDescriptorType; Configuration */
  735. 0x19, /* __u16 wTotalLength; */
  736. 0x00,
  737. 0x01, /* __u8 bNumInterfaces; */
  738. 0x01, /* __u8 bConfigurationValue; */
  739. 0x00, /* __u8 iConfiguration; */
  740. 0x40, /* __u8 bmAttributes;
  741. Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
  742. 0x00, /* __u8 MaxPower; */
  743. /* interface */
  744. 0x09, /* __u8 if_bLength; */
  745. 0x04, /* __u8 if_bDescriptorType; Interface */
  746. 0x00, /* __u8 if_bInterfaceNumber; */
  747. 0x00, /* __u8 if_bAlternateSetting; */
  748. 0x01, /* __u8 if_bNumEndpoints; */
  749. 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
  750. 0x00, /* __u8 if_bInterfaceSubClass; */
  751. 0x00, /* __u8 if_bInterfaceProtocol; */
  752. 0x00, /* __u8 if_iInterface; */
  753. /* endpoint */
  754. 0x07, /* __u8 ep_bLength; */
  755. 0x05, /* __u8 ep_bDescriptorType; Endpoint */
  756. 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
  757. 0x03, /* __u8 ep_bmAttributes; Interrupt */
  758. 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
  759. 0x00,
  760. 0xff /* __u8 ep_bInterval; 255 ms */
  761. };
  762. static unsigned char root_hub_str_index0[] =
  763. {
  764. 0x04, /* __u8 bLength; */
  765. 0x03, /* __u8 bDescriptorType; String-descriptor */
  766. 0x09, /* __u8 lang ID */
  767. 0x04, /* __u8 lang ID */
  768. };
  769. static unsigned char root_hub_str_index1[] =
  770. {
  771. 28, /* __u8 bLength; */
  772. 0x03, /* __u8 bDescriptorType; String-descriptor */
  773. 'O', /* __u8 Unicode */
  774. 0, /* __u8 Unicode */
  775. 'H', /* __u8 Unicode */
  776. 0, /* __u8 Unicode */
  777. 'C', /* __u8 Unicode */
  778. 0, /* __u8 Unicode */
  779. 'I', /* __u8 Unicode */
  780. 0, /* __u8 Unicode */
  781. ' ', /* __u8 Unicode */
  782. 0, /* __u8 Unicode */
  783. 'R', /* __u8 Unicode */
  784. 0, /* __u8 Unicode */
  785. 'o', /* __u8 Unicode */
  786. 0, /* __u8 Unicode */
  787. 'o', /* __u8 Unicode */
  788. 0, /* __u8 Unicode */
  789. 't', /* __u8 Unicode */
  790. 0, /* __u8 Unicode */
  791. ' ', /* __u8 Unicode */
  792. 0, /* __u8 Unicode */
  793. 'H', /* __u8 Unicode */
  794. 0, /* __u8 Unicode */
  795. 'u', /* __u8 Unicode */
  796. 0, /* __u8 Unicode */
  797. 'b', /* __u8 Unicode */
  798. 0, /* __u8 Unicode */
  799. };
  800. /* Hub class-specific descriptor is constructed dynamically */
  801. /*-------------------------------------------------------------------------*/
  802. #define OK(x) len = (x); break
  803. #ifdef DEBUG
  804. #define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
  805. #define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
  806. #else
  807. #define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
  808. #define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
  809. #endif
  810. #define RD_RH_STAT roothub_status(&gohci)
  811. #define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
  812. /* request to virtual root hub */
  813. static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  814. int transfer_len, struct devrequest *cmd)
  815. {
  816. void * data = buffer;
  817. int leni = transfer_len;
  818. int len = 0;
  819. int stat = 0;
  820. __u32 datab[4];
  821. __u8 *data_buf = (__u8 *)datab;
  822. __u16 bmRType_bReq;
  823. __u16 wValue;
  824. __u16 wIndex;
  825. __u16 wLength;
  826. #ifdef DEBUG
  827. urb_priv.actual_length = 0;
  828. pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
  829. #else
  830. wait_ms(1);
  831. #endif
  832. if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
  833. info("Root-Hub submit IRQ: NOT implemented");
  834. return 0;
  835. }
  836. bmRType_bReq = cmd->requesttype | (cmd->request << 8);
  837. wValue = m16_swap (cmd->value);
  838. wIndex = m16_swap (cmd->index);
  839. wLength = m16_swap (cmd->length);
  840. info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
  841. dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
  842. switch (bmRType_bReq) {
  843. /* Request Destination:
  844. without flags: Device,
  845. RH_INTERFACE: interface,
  846. RH_ENDPOINT: endpoint,
  847. RH_CLASS means HUB here,
  848. RH_OTHER | RH_CLASS almost ever means HUB_PORT here
  849. */
  850. case RH_GET_STATUS:
  851. *(__u16 *) data_buf = m16_swap (1); OK (2);
  852. case RH_GET_STATUS | RH_INTERFACE:
  853. *(__u16 *) data_buf = m16_swap (0); OK (2);
  854. case RH_GET_STATUS | RH_ENDPOINT:
  855. *(__u16 *) data_buf = m16_swap (0); OK (2);
  856. case RH_GET_STATUS | RH_CLASS:
  857. *(__u32 *) data_buf = m32_swap (
  858. RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
  859. OK (4);
  860. case RH_GET_STATUS | RH_OTHER | RH_CLASS:
  861. *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
  862. case RH_CLEAR_FEATURE | RH_ENDPOINT:
  863. switch (wValue) {
  864. case (RH_ENDPOINT_STALL): OK (0);
  865. }
  866. break;
  867. case RH_CLEAR_FEATURE | RH_CLASS:
  868. switch (wValue) {
  869. case RH_C_HUB_LOCAL_POWER:
  870. OK(0);
  871. case (RH_C_HUB_OVER_CURRENT):
  872. WR_RH_STAT(RH_HS_OCIC); OK (0);
  873. }
  874. break;
  875. case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
  876. switch (wValue) {
  877. case (RH_PORT_ENABLE):
  878. WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
  879. case (RH_PORT_SUSPEND):
  880. WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
  881. case (RH_PORT_POWER):
  882. WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
  883. case (RH_C_PORT_CONNECTION):
  884. WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
  885. case (RH_C_PORT_ENABLE):
  886. WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
  887. case (RH_C_PORT_SUSPEND):
  888. WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
  889. case (RH_C_PORT_OVER_CURRENT):
  890. WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
  891. case (RH_C_PORT_RESET):
  892. WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
  893. }
  894. break;
  895. case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
  896. switch (wValue) {
  897. case (RH_PORT_SUSPEND):
  898. WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
  899. case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
  900. if (RD_RH_PORTSTAT & RH_PS_CCS)
  901. WR_RH_PORTSTAT (RH_PS_PRS);
  902. OK (0);
  903. case (RH_PORT_POWER):
  904. WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
  905. case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
  906. if (RD_RH_PORTSTAT & RH_PS_CCS)
  907. WR_RH_PORTSTAT (RH_PS_PES );
  908. OK (0);
  909. }
  910. break;
  911. case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
  912. case RH_GET_DESCRIPTOR:
  913. switch ((wValue & 0xff00) >> 8) {
  914. case (0x01): /* device descriptor */
  915. len = min_t(unsigned int,
  916. leni,
  917. min_t(unsigned int,
  918. sizeof (root_hub_dev_des),
  919. wLength));
  920. data_buf = root_hub_dev_des; OK(len);
  921. case (0x02): /* configuration descriptor */
  922. len = min_t(unsigned int,
  923. leni,
  924. min_t(unsigned int,
  925. sizeof (root_hub_config_des),
  926. wLength));
  927. data_buf = root_hub_config_des; OK(len);
  928. case (0x03): /* string descriptors */
  929. if(wValue==0x0300) {
  930. len = min_t(unsigned int,
  931. leni,
  932. min_t(unsigned int,
  933. sizeof (root_hub_str_index0),
  934. wLength));
  935. data_buf = root_hub_str_index0;
  936. OK(len);
  937. }
  938. if(wValue==0x0301) {
  939. len = min_t(unsigned int,
  940. leni,
  941. min_t(unsigned int,
  942. sizeof (root_hub_str_index1),
  943. wLength));
  944. data_buf = root_hub_str_index1;
  945. OK(len);
  946. }
  947. default:
  948. stat = USB_ST_STALLED;
  949. }
  950. break;
  951. case RH_GET_DESCRIPTOR | RH_CLASS:
  952. {
  953. __u32 temp = roothub_a (&gohci);
  954. data_buf [0] = 9; /* min length; */
  955. data_buf [1] = 0x29;
  956. data_buf [2] = temp & RH_A_NDP;
  957. data_buf [3] = 0;
  958. if (temp & RH_A_PSM) /* per-port power switching? */
  959. data_buf [3] |= 0x1;
  960. if (temp & RH_A_NOCP) /* no overcurrent reporting? */
  961. data_buf [3] |= 0x10;
  962. else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
  963. data_buf [3] |= 0x8;
  964. /* corresponds to data_buf[4-7] */
  965. datab [1] = 0;
  966. data_buf [5] = (temp & RH_A_POTPGT) >> 24;
  967. temp = roothub_b (&gohci);
  968. data_buf [7] = temp & RH_B_DR;
  969. if (data_buf [2] < 7) {
  970. data_buf [8] = 0xff;
  971. } else {
  972. data_buf [0] += 2;
  973. data_buf [8] = (temp & RH_B_DR) >> 8;
  974. data_buf [10] = data_buf [9] = 0xff;
  975. }
  976. len = min_t(unsigned int, leni,
  977. min_t(unsigned int, data_buf [0], wLength));
  978. OK (len);
  979. }
  980. case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
  981. case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
  982. default:
  983. dbg ("unsupported root hub command");
  984. stat = USB_ST_STALLED;
  985. }
  986. #ifdef DEBUG
  987. ohci_dump_roothub (&gohci, 1);
  988. #else
  989. wait_ms(1);
  990. #endif
  991. len = min_t(int, len, leni);
  992. if (data != data_buf)
  993. memcpy (data, data_buf, len);
  994. dev->act_len = len;
  995. dev->status = stat;
  996. #ifdef DEBUG
  997. if (transfer_len)
  998. urb_priv.actual_length = transfer_len;
  999. pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
  1000. #else
  1001. wait_ms(1);
  1002. #endif
  1003. return stat;
  1004. }
  1005. /*-------------------------------------------------------------------------*/
  1006. /* common code for handling submit messages - used for all but root hub */
  1007. /* accesses. */
  1008. int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1009. int transfer_len, struct devrequest *setup, int interval)
  1010. {
  1011. int stat = 0;
  1012. int maxsize = usb_maxpacket(dev, pipe);
  1013. int timeout;
  1014. #ifdef DEBUG
  1015. urb_priv.actual_length = 0;
  1016. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1017. #else
  1018. wait_ms(1);
  1019. #endif
  1020. if (!maxsize) {
  1021. err("submit_common_message: pipesize for pipe %lx is zero",
  1022. pipe);
  1023. return -1;
  1024. }
  1025. if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
  1026. err("sohci_submit_job failed");
  1027. return -1;
  1028. }
  1029. wait_ms(10);
  1030. /* ohci_dump_status(&gohci); */
  1031. /* allow more time for a BULK device to react - some are slow */
  1032. #define BULK_TO 2000 /* timeout in milliseconds */
  1033. if (usb_pipetype (pipe) == PIPE_BULK)
  1034. timeout = BULK_TO;
  1035. else
  1036. timeout = 100;
  1037. /* wait for it to complete */
  1038. for (;;) {
  1039. /* check whether the controller is done */
  1040. stat = hc_interrupt();
  1041. if (stat < 0) {
  1042. stat = 1;
  1043. break;
  1044. }
  1045. if (stat >= 0 && stat != 0xff) {
  1046. /* 0xff is returned for an SF-interrupt */
  1047. break;
  1048. }
  1049. if (--timeout) {
  1050. wait_ms(1);
  1051. } else {
  1052. err("CTL:TIMEOUT");
  1053. stat = 1;
  1054. break;
  1055. }
  1056. }
  1057. dev->status = stat;
  1058. dev->act_len = transfer_len;
  1059. #ifdef DEBUG
  1060. pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
  1061. #else
  1062. wait_ms(1);
  1063. #endif
  1064. /* free TDs in urb_priv */
  1065. urb_free_priv (&urb_priv);
  1066. return 0;
  1067. }
  1068. /* submit routines called from usb.c */
  1069. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1070. int transfer_len)
  1071. {
  1072. info("submit_bulk_msg");
  1073. return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
  1074. }
  1075. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1076. int transfer_len, struct devrequest *setup)
  1077. {
  1078. int maxsize = usb_maxpacket(dev, pipe);
  1079. info("submit_control_msg");
  1080. #ifdef DEBUG
  1081. urb_priv.actual_length = 0;
  1082. pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
  1083. #else
  1084. wait_ms(1);
  1085. #endif
  1086. if (!maxsize) {
  1087. err("submit_control_message: pipesize for pipe %lx is zero",
  1088. pipe);
  1089. return -1;
  1090. }
  1091. if (((pipe >> 8) & 0x7f) == gohci.rh.devnum)
  1092. /* root hub - redirect */
  1093. return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
  1094. setup);
  1095. return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
  1096. }
  1097. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1098. int transfer_len, int interval)
  1099. {
  1100. info("submit_int_msg");
  1101. return -1;
  1102. }
  1103. /*-------------------------------------------------------------------------*
  1104. * HC functions
  1105. *-------------------------------------------------------------------------*/
  1106. /* reset the HC and BUS */
  1107. static int hc_reset (ohci_t *ohci)
  1108. {
  1109. int timeout = 30;
  1110. int smm_timeout = 50; /* 0,5 sec */
  1111. if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
  1112. writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
  1113. info("USB HC TakeOver from SMM");
  1114. while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
  1115. wait_ms (10);
  1116. if (--smm_timeout == 0) {
  1117. err("USB HC TakeOver failed!");
  1118. return -1;
  1119. }
  1120. }
  1121. }
  1122. /* Disable HC interrupts */
  1123. writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
  1124. dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
  1125. ohci->slot_name,
  1126. readl (&ohci->regs->control));
  1127. /* Reset USB (needed by some controllers) */
  1128. writel (0, &ohci->regs->control);
  1129. /* HC Reset requires max 10 us delay */
  1130. writel (OHCI_HCR, &ohci->regs->cmdstatus);
  1131. while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
  1132. if (--timeout == 0) {
  1133. err("USB HC reset timed out!");
  1134. return -1;
  1135. }
  1136. udelay (1);
  1137. }
  1138. return 0;
  1139. }
  1140. /*-------------------------------------------------------------------------*/
  1141. /* Start an OHCI controller, set the BUS operational
  1142. * enable interrupts
  1143. * connect the virtual root hub */
  1144. static int hc_start (ohci_t * ohci)
  1145. {
  1146. __u32 mask;
  1147. unsigned int fminterval;
  1148. ohci->disabled = 1;
  1149. /* Tell the controller where the control and bulk lists are
  1150. * The lists are empty now. */
  1151. writel (0, &ohci->regs->ed_controlhead);
  1152. writel (0, &ohci->regs->ed_bulkhead);
  1153. writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
  1154. fminterval = 0x2edf;
  1155. writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
  1156. fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
  1157. writel (fminterval, &ohci->regs->fminterval);
  1158. writel (0x628, &ohci->regs->lsthresh);
  1159. /* start controller operations */
  1160. ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
  1161. ohci->disabled = 0;
  1162. writel (ohci->hc_control, &ohci->regs->control);
  1163. /* Choose the interrupts we care about now, others later on demand */
  1164. mask = OHCI_INTR_MIE | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
  1165. writel (mask, &ohci->regs->intrstatus);
  1166. #ifdef OHCI_USE_NPS
  1167. /* required for AMD-756 and some Mac platforms */
  1168. writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
  1169. &ohci->regs->roothub.a);
  1170. writel (RH_HS_LPSC, &ohci->regs->roothub.status);
  1171. #endif /* OHCI_USE_NPS */
  1172. #define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
  1173. /* POTPGT delay is bits 24-31, in 2 ms units. */
  1174. mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
  1175. /* connect the virtual root hub */
  1176. ohci->rh.devnum = 0;
  1177. return 0;
  1178. }
  1179. /*-------------------------------------------------------------------------*/
  1180. /* an interrupt happens */
  1181. static int
  1182. hc_interrupt (void)
  1183. {
  1184. ohci_t *ohci = &gohci;
  1185. struct ohci_regs *regs = ohci->regs;
  1186. int ints;
  1187. int stat = -1;
  1188. if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
  1189. ints = OHCI_INTR_WDH;
  1190. } else {
  1191. ints = readl (&regs->intrstatus);
  1192. }
  1193. /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
  1194. if (ints & OHCI_INTR_UE) {
  1195. ohci->disabled++;
  1196. err ("OHCI Unrecoverable Error, controller usb-%s disabled",
  1197. ohci->slot_name);
  1198. /* e.g. due to PCI Master/Target Abort */
  1199. #ifdef DEBUG
  1200. ohci_dump (ohci, 1);
  1201. #else
  1202. wait_ms(1);
  1203. #endif
  1204. /* FIXME: be optimistic, hope that bug won't repeat often. */
  1205. /* Make some non-interrupt context restart the controller. */
  1206. /* Count and limit the retries though; either hardware or */
  1207. /* software errors can go forever... */
  1208. hc_reset (ohci);
  1209. return -1;
  1210. }
  1211. if (ints & OHCI_INTR_WDH) {
  1212. wait_ms(1);
  1213. writel (OHCI_INTR_WDH, &regs->intrdisable);
  1214. stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
  1215. writel (OHCI_INTR_WDH, &regs->intrenable);
  1216. }
  1217. if (ints & OHCI_INTR_SO) {
  1218. dbg("USB Schedule overrun\n");
  1219. writel (OHCI_INTR_SO, &regs->intrenable);
  1220. stat = -1;
  1221. }
  1222. /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
  1223. if (ints & OHCI_INTR_SF) {
  1224. unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
  1225. wait_ms(1);
  1226. writel (OHCI_INTR_SF, &regs->intrdisable);
  1227. if (ohci->ed_rm_list[frame] != NULL)
  1228. writel (OHCI_INTR_SF, &regs->intrenable);
  1229. stat = 0xff;
  1230. }
  1231. writel (ints, &regs->intrstatus);
  1232. return stat;
  1233. }
  1234. /*-------------------------------------------------------------------------*/
  1235. /*-------------------------------------------------------------------------*/
  1236. /* De-allocate all resources.. */
  1237. static void hc_release_ohci (ohci_t *ohci)
  1238. {
  1239. dbg ("USB HC release ohci usb-%s", ohci->slot_name);
  1240. if (!ohci->disabled)
  1241. hc_reset (ohci);
  1242. }
  1243. /*-------------------------------------------------------------------------*/
  1244. /*
  1245. * low level initalisation routine, called from usb.c
  1246. */
  1247. static char ohci_inited = 0;
  1248. int usb_lowlevel_init(void)
  1249. {
  1250. S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
  1251. S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
  1252. /*
  1253. * Set the 48 MHz UPLL clocking. Values are taken from
  1254. * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
  1255. */
  1256. clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
  1257. gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
  1258. /*
  1259. * Enable USB host clock.
  1260. */
  1261. clk_power->CLKCON |= (1 << 4);
  1262. memset (&gohci, 0, sizeof (ohci_t));
  1263. memset (&urb_priv, 0, sizeof (urb_priv_t));
  1264. /* align the storage */
  1265. if ((__u32)&ghcca[0] & 0xff) {
  1266. err("HCCA not aligned!!");
  1267. return -1;
  1268. }
  1269. phcca = &ghcca[0];
  1270. info("aligned ghcca %p", phcca);
  1271. memset(&ohci_dev, 0, sizeof(struct ohci_device));
  1272. if ((__u32)&ohci_dev.ed[0] & 0x7) {
  1273. err("EDs not aligned!!");
  1274. return -1;
  1275. }
  1276. memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
  1277. if ((__u32)gtd & 0x7) {
  1278. err("TDs not aligned!!");
  1279. return -1;
  1280. }
  1281. ptd = gtd;
  1282. gohci.hcca = phcca;
  1283. memset (phcca, 0, sizeof (struct ohci_hcca));
  1284. gohci.disabled = 1;
  1285. gohci.sleeping = 0;
  1286. gohci.irq = -1;
  1287. gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
  1288. gohci.flags = 0;
  1289. gohci.slot_name = "s3c2400";
  1290. if (hc_reset (&gohci) < 0) {
  1291. hc_release_ohci (&gohci);
  1292. /* Initialization failed */
  1293. clk_power->CLKCON &= ~(1 << 4);
  1294. return -1;
  1295. }
  1296. /* FIXME this is a second HC reset; why?? */
  1297. writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
  1298. wait_ms (10);
  1299. if (hc_start (&gohci) < 0) {
  1300. err ("can't start usb-%s", gohci.slot_name);
  1301. hc_release_ohci (&gohci);
  1302. /* Initialization failed */
  1303. clk_power->CLKCON &= ~(1 << 4);
  1304. return -1;
  1305. }
  1306. #ifdef DEBUG
  1307. ohci_dump (&gohci, 1);
  1308. #else
  1309. wait_ms(1);
  1310. #endif
  1311. ohci_inited = 1;
  1312. return 0;
  1313. }
  1314. int usb_lowlevel_stop(void)
  1315. {
  1316. S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
  1317. /* this gets called really early - before the controller has */
  1318. /* even been initialized! */
  1319. if (!ohci_inited)
  1320. return 0;
  1321. /* TODO release any interrupts, etc. */
  1322. /* call hc_release_ohci() here ? */
  1323. hc_reset (&gohci);
  1324. /* may not want to do this */
  1325. clk_power->CLKCON &= ~(1 << 4);
  1326. return 0;
  1327. }
  1328. #endif /* CONFIG_USB_OHCI */