M54455EVB.h 13 KB

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  1. /*
  2. * Configuation settings for the Freescale MCF54455 EVB board.
  3. *
  4. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * board/config.h - configuration options, board specific
  27. */
  28. #ifndef _M54455EVB_H
  29. #define _M54455EVB_H
  30. /*
  31. * High Level Configuration Options
  32. * (easy to change)
  33. */
  34. #define CONFIG_MCF5445x /* define processor family */
  35. #define CONFIG_M54455 /* define processor type */
  36. #define CONFIG_M54455EVB /* M54455EVB board */
  37. #define CONFIG_MCFUART
  38. #define CFG_UART_PORT (0)
  39. #define CONFIG_BAUDRATE 115200
  40. #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  41. #undef CONFIG_WATCHDOG
  42. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  43. /*
  44. * BOOTP options
  45. */
  46. #define CONFIG_BOOTP_BOOTFILESIZE
  47. #define CONFIG_BOOTP_BOOTPATH
  48. #define CONFIG_BOOTP_GATEWAY
  49. #define CONFIG_BOOTP_HOSTNAME
  50. /* Command line configuration */
  51. #include <config_cmd_default.h>
  52. #define CONFIG_CMD_BOOTD
  53. #define CONFIG_CMD_CACHE
  54. #define CONFIG_CMD_DATE
  55. #define CONFIG_CMD_DHCP
  56. #define CONFIG_CMD_ELF
  57. #define CONFIG_CMD_EXT2
  58. #define CONFIG_CMD_FAT
  59. #define CONFIG_CMD_FLASH
  60. #define CONFIG_CMD_I2C
  61. #define CONFIG_CMD_IDE
  62. #define CONFIG_CMD_JFFS2
  63. #define CONFIG_CMD_MEMORY
  64. #define CONFIG_CMD_MISC
  65. #define CONFIG_CMD_MII
  66. #define CONFIG_CMD_NET
  67. #undef CONFIG_CMD_PCI
  68. #define CONFIG_CMD_PING
  69. #define CONFIG_CMD_REGINFO
  70. #define CONFIG_CMD_SPI
  71. #undef CONFIG_CMD_LOADB
  72. #undef CONFIG_CMD_LOADS
  73. /* Network configuration */
  74. #define CONFIG_MCFFEC
  75. #ifdef CONFIG_MCFFEC
  76. # define CONFIG_NET_MULTI 1
  77. # define CONFIG_MII 1
  78. # define CONFIG_MII_INIT 1
  79. # define CFG_DISCOVER_PHY
  80. # define CFG_RX_ETH_BUFFER 8
  81. # define CFG_FAULT_ECHO_LINK_DOWN
  82. # define CFG_FEC0_PINMUX 0
  83. # define CFG_FEC1_PINMUX 0
  84. # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
  85. # define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
  86. # define MCFFEC_TOUT_LOOP 50000
  87. # define CONFIG_HAS_ETH1
  88. # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
  89. # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
  90. # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
  91. # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
  92. # define CONFIG_ETHPRIME "FEC0"
  93. # define CONFIG_IPADDR 192.162.1.2
  94. # define CONFIG_NETMASK 255.255.255.0
  95. # define CONFIG_SERVERIP 192.162.1.1
  96. # define CONFIG_GATEWAYIP 192.162.1.1
  97. # define CONFIG_OVERWRITE_ETHADDR_ONCE
  98. /* If CFG_DISCOVER_PHY is not defined - hardcoded */
  99. # ifndef CFG_DISCOVER_PHY
  100. # define FECDUPLEX FULL
  101. # define FECSPEED _100BASET
  102. # else
  103. # ifndef CFG_FAULT_ECHO_LINK_DOWN
  104. # define CFG_FAULT_ECHO_LINK_DOWN
  105. # endif
  106. # endif /* CFG_DISCOVER_PHY */
  107. #endif
  108. #define CONFIG_HOSTNAME M54455EVB
  109. #ifdef CFG_STMICRO_BOOT
  110. /* ST Micro serial flash */
  111. #define CFG_LOAD_ADDR2 0x40010013
  112. #define CONFIG_EXTRA_ENV_SETTINGS \
  113. "netdev=eth0\0" \
  114. "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
  115. "loadaddr=0x40010000\0" \
  116. "sbfhdr=sbfhdr.bin\0" \
  117. "uboot=u-boot.bin\0" \
  118. "load=tftp ${loadaddr} ${sbfhdr};" \
  119. "tftp " MK_STR(CFG_LOAD_ADDR2) " ${uboot} \0" \
  120. "upd=run load; run prog\0" \
  121. "prog=sf probe 0:1 10000 1;" \
  122. "sf erase 0 30000;" \
  123. "sf write ${loadaddr} 0 0x30000;" \
  124. "save\0" \
  125. ""
  126. #else
  127. /* Atmel and Intel */
  128. #ifdef CFG_ATMEL_BOOT
  129. # define CFG_UBOOT_END 0x0403FFFF
  130. #elif defined(CFG_INTEL_BOOT)
  131. # define CFG_UBOOT_END 0x3FFFF
  132. #endif
  133. #define CONFIG_EXTRA_ENV_SETTINGS \
  134. "netdev=eth0\0" \
  135. "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \
  136. "loadaddr=0x40010000\0" \
  137. "uboot=u-boot.bin\0" \
  138. "load=tftp ${loadaddr} ${uboot}\0" \
  139. "upd=run load; run prog\0" \
  140. "prog=prot off " MK_STR(CFG_FLASH_BASE) \
  141. " " MK_STR(CFG_UBOOT_END) ";" \
  142. "era " MK_STR(CFG_FLASH_BASE) " " \
  143. MK_STR(CFG_UBOOT_END) ";" \
  144. "cp.b ${loadaddr} " MK_STR(CFG_FLASH_BASE)\
  145. " ${filesize}; save\0" \
  146. ""
  147. #endif
  148. /* ATA configuration */
  149. #define CONFIG_ISO_PARTITION
  150. #define CONFIG_DOS_PARTITION
  151. #define CONFIG_IDE_RESET 1
  152. #define CONFIG_IDE_PREINIT 1
  153. #define CONFIG_ATAPI
  154. #undef CONFIG_LBA48
  155. #define CFG_IDE_MAXBUS 1
  156. #define CFG_IDE_MAXDEVICE 2
  157. #define CFG_ATA_BASE_ADDR 0x90000000
  158. #define CFG_ATA_IDE0_OFFSET 0
  159. #define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
  160. #define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
  161. #define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
  162. #define CFG_ATA_STRIDE 4 /* Interval between registers */
  163. #define _IO_BASE 0
  164. /* Realtime clock */
  165. #define CONFIG_MCFRTC
  166. #undef RTC_DEBUG
  167. #define CFG_RTC_OSCILLATOR (32 * CFG_HZ)
  168. /* Timer */
  169. #define CONFIG_MCFTMR
  170. #undef CONFIG_MCFPIT
  171. /* I2c */
  172. #define CONFIG_FSL_I2C
  173. #define CONFIG_HARD_I2C /* I2C with hardware support */
  174. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  175. #define CFG_I2C_SPEED 80000 /* I2C speed and slave address */
  176. #define CFG_I2C_SLAVE 0x7F
  177. #define CFG_I2C_OFFSET 0x58000
  178. #define CFG_IMMR CFG_MBAR
  179. /* DSPI and Serial Flash */
  180. #define CONFIG_CF_DSPI
  181. #define CONFIG_HARD_SPI
  182. #define CFG_SER_FLASH_BASE 0x01000000
  183. #define CFG_SBFHDR_SIZE 0x13
  184. #ifdef CONFIG_CMD_SPI
  185. # define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \
  186. DSPI_DCTAR_CPOL | \
  187. DSPI_DCTAR_CPHA | \
  188. DSPI_DCTAR_PCSSCK_1CLK | \
  189. DSPI_DCTAR_PASC(0) | \
  190. DSPI_DCTAR_PDT(0) | \
  191. DSPI_DCTAR_CSSCK(0) | \
  192. DSPI_DCTAR_ASC(0) | \
  193. DSPI_DCTAR_PBR(0) | \
  194. DSPI_DCTAR_DT(1) | \
  195. DSPI_DCTAR_BR(1))
  196. #endif
  197. /* PCI */
  198. #ifdef CONFIG_CMD_PCI
  199. #define CONFIG_PCI 1
  200. #define CONFIG_PCI_PNP 1
  201. #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  202. #define CFG_PCI_CACHE_LINE_SIZE 4
  203. #define CFG_PCI_MEM_BUS 0xA0000000
  204. #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
  205. #define CFG_PCI_MEM_SIZE 0x10000000
  206. #define CFG_PCI_IO_BUS 0xB1000000
  207. #define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS
  208. #define CFG_PCI_IO_SIZE 0x01000000
  209. #define CFG_PCI_CFG_BUS 0xB0000000
  210. #define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS
  211. #define CFG_PCI_CFG_SIZE 0x01000000
  212. #endif
  213. /* FPGA - Spartan 2 */
  214. /* experiment
  215. #define CONFIG_FPGA CFG_SPARTAN3
  216. #define CONFIG_FPGA_COUNT 1
  217. #define CFG_FPGA_PROG_FEEDBACK
  218. #define CFG_FPGA_CHECK_CTRLC
  219. */
  220. /* Input, PCI, Flexbus, and VCO */
  221. #define CONFIG_EXTRA_CLOCK
  222. #define CONFIG_PRAM 2048 /* 2048 KB */
  223. #define CFG_PROMPT "-> "
  224. #define CFG_LONGHELP /* undef to save memory */
  225. #if defined(CONFIG_CMD_KGDB)
  226. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  227. #else
  228. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  229. #endif
  230. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  231. #define CFG_MAXARGS 16 /* max number of command args */
  232. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  233. #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000)
  234. #define CFG_HZ 1000
  235. #define CFG_MBAR 0xFC000000
  236. /*
  237. * Low Level Configuration Settings
  238. * (address mappings, register initial values, etc.)
  239. * You should know what you are doing if you make changes here.
  240. */
  241. /*-----------------------------------------------------------------------
  242. * Definitions for initial stack pointer and data area (in DPRAM)
  243. */
  244. #define CFG_INIT_RAM_ADDR 0x80000000
  245. #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
  246. #define CFG_INIT_RAM_CTRL 0x221
  247. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  248. #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 32)
  249. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  250. #define CFG_SBFHDR_DATA_OFFSET (CFG_INIT_RAM_END - 32)
  251. /*-----------------------------------------------------------------------
  252. * Start addresses for the final memory configuration
  253. * (Set up by the startup code)
  254. * Please note that CFG_SDRAM_BASE _must_ start at 0
  255. */
  256. #define CFG_SDRAM_BASE 0x40000000
  257. #define CFG_SDRAM_BASE1 0x48000000
  258. #define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */
  259. #define CFG_SDRAM_CFG1 0x65311610
  260. #define CFG_SDRAM_CFG2 0x59670000
  261. #define CFG_SDRAM_CTRL 0xEA0B2000
  262. #define CFG_SDRAM_EMOD 0x40010000
  263. #define CFG_SDRAM_MODE 0x00010033
  264. #define CFG_SDRAM_DRV_STRENGTH 0xAA
  265. #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400
  266. #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20)
  267. #ifdef CONFIG_CF_SBF
  268. # define CFG_MONITOR_BASE (TEXT_BASE + 0x400)
  269. #else
  270. # define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
  271. #endif
  272. #define CFG_BOOTPARAMS_LEN 64*1024
  273. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  274. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  275. /*
  276. * For booting Linux, the board info and command line data
  277. * have to be in the first 8 MB of memory, since this is
  278. * the maximum mapped by the Linux kernel during initialization ??
  279. */
  280. /* Initial Memory map for Linux */
  281. #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
  282. /*
  283. * Configuration for environment
  284. * Environment is embedded in u-boot in the second sector of the flash
  285. */
  286. #ifdef CONFIG_CF_SBF
  287. # define CFG_ENV_IS_IN_SPI_FLASH
  288. # define CFG_ENV_SPI_CS 1
  289. #else
  290. # define CFG_ENV_IS_IN_FLASH 1
  291. #endif
  292. #undef CONFIG_ENV_OVERWRITE
  293. #undef CFG_ENV_IS_EMBEDDED
  294. /*-----------------------------------------------------------------------
  295. * FLASH organization
  296. */
  297. #ifdef CFG_STMICRO_BOOT
  298. # define CFG_FLASH_BASE CFG_SER_FLASH_BASE
  299. # define CFG_FLASH0_BASE CFG_SER_FLASH_BASE
  300. # define CFG_FLASH1_BASE CFG_CS0_BASE
  301. # define CFG_FLASH2_BASE CFG_CS1_BASE
  302. # define CFG_ENV_OFFSET 0x30000
  303. # define CFG_ENV_SIZE 0x2000
  304. # define CFG_ENV_SECT_SIZE 0x10000
  305. #endif
  306. #ifdef CFG_ATMEL_BOOT
  307. # define CFG_FLASH_BASE CFG_CS0_BASE
  308. # define CFG_FLASH0_BASE CFG_CS0_BASE
  309. # define CFG_FLASH1_BASE CFG_CS1_BASE
  310. # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
  311. # define CFG_ENV_SECT_SIZE 0x2000
  312. #endif
  313. #ifdef CFG_INTEL_BOOT
  314. # define CFG_FLASH_BASE CFG_CS0_BASE
  315. # define CFG_FLASH0_BASE CFG_CS0_BASE
  316. # define CFG_FLASH1_BASE CFG_CS1_BASE
  317. # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000)
  318. # define CFG_ENV_SIZE 0x2000
  319. # define CFG_ENV_SECT_SIZE 0x20000
  320. #endif
  321. #define CFG_FLASH_CFI
  322. #ifdef CFG_FLASH_CFI
  323. # define CONFIG_FLASH_CFI_DRIVER 1
  324. # define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
  325. # define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
  326. # define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  327. # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
  328. # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  329. # define CFG_FLASH_CHECKSUM
  330. # define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE }
  331. # define CONFIG_FLASH_CFI_LEGACY
  332. #ifdef CONFIG_FLASH_CFI_LEGACY
  333. # define CFG_ATMEL_REGION 4
  334. # define CFG_ATMEL_TOTALSECT 11
  335. # define CFG_ATMEL_SECT {1, 2, 1, 7}
  336. # define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
  337. #endif
  338. #endif
  339. #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  340. #define CFG_FLASH_CHECKSUM
  341. /*
  342. * This is setting for JFFS2 support in u-boot.
  343. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  344. */
  345. #ifdef CONFIG_CMD_JFFS2
  346. #ifdef CF_STMICRO_BOOT
  347. # define CONFIG_JFFS2_DEV "nor1"
  348. # define CONFIG_JFFS2_PART_SIZE 0x01000000
  349. # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH2_BASE + 0x500000)
  350. #endif
  351. #ifdef CFG_ATMEL_BOOT
  352. # define CONFIG_JFFS2_DEV "nor1"
  353. # define CONFIG_JFFS2_PART_SIZE 0x01000000
  354. # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000)
  355. #endif
  356. #ifdef CFG_INTEL_BOOT
  357. # define CONFIG_JFFS2_DEV "nor0"
  358. # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
  359. # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000)
  360. #endif
  361. #endif
  362. /*-----------------------------------------------------------------------
  363. * Cache Configuration
  364. */
  365. #define CFG_CACHELINE_SIZE 16
  366. /*-----------------------------------------------------------------------
  367. * Memory bank definitions
  368. */
  369. /*
  370. * CS0 - NOR Flash 1, 2, 4, or 8MB
  371. * CS1 - CompactFlash and registers
  372. * CS2 - CPLD
  373. * CS3 - FPGA
  374. * CS4 - Available
  375. * CS5 - Available
  376. */
  377. #if defined(CFG_ATMEL_BOOT) || defined(CFG_STMICRO_BOOT)
  378. /* Atmel Flash */
  379. #define CFG_CS0_BASE 0x04000000
  380. #define CFG_CS0_MASK 0x00070001
  381. #define CFG_CS0_CTRL 0x00001140
  382. /* Intel Flash */
  383. #define CFG_CS1_BASE 0x00000000
  384. #define CFG_CS1_MASK 0x01FF0001
  385. #define CFG_CS1_CTRL 0x00000D60
  386. #define CFG_ATMEL_BASE CFG_CS0_BASE
  387. #else
  388. /* Intel Flash */
  389. #define CFG_CS0_BASE 0x00000000
  390. #define CFG_CS0_MASK 0x01FF0001
  391. #define CFG_CS0_CTRL 0x00000D60
  392. /* Atmel Flash */
  393. #define CFG_CS1_BASE 0x04000000
  394. #define CFG_CS1_MASK 0x00070001
  395. #define CFG_CS1_CTRL 0x00001140
  396. #define CFG_ATMEL_BASE CFG_CS1_BASE
  397. #endif
  398. /* CPLD */
  399. #define CFG_CS2_BASE 0x08000000
  400. #define CFG_CS2_MASK 0x00070001
  401. #define CFG_CS2_CTRL 0x003f1140
  402. /* FPGA */
  403. #define CFG_CS3_BASE 0x09000000
  404. #define CFG_CS3_MASK 0x00070001
  405. #define CFG_CS3_CTRL 0x00000020
  406. #endif /* _M54455EVB_H */