flash.c 11 KB

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  1. /*
  2. * (C) Copyright 2003-2004
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2004
  6. * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  7. *
  8. * Modified for the CMC PU2 by (C) Copyright 2004 Gary Jennejohn
  9. * garyj@denx.de
  10. *
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. #include <common.h>
  30. flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  31. /*
  32. * CPU to flash interface is 32-bit, so make declaration accordingly
  33. */
  34. typedef unsigned short FLASH_PORT_WIDTH;
  35. typedef volatile unsigned short FLASH_PORT_WIDTHV;
  36. #define FPW FLASH_PORT_WIDTH
  37. #define FPWV FLASH_PORT_WIDTHV
  38. #define FLASH_CYCLE1 0x0555
  39. #define FLASH_CYCLE2 0x02aa
  40. /*-----------------------------------------------------------------------
  41. * Functions
  42. */
  43. static ulong flash_get_size(FPWV *addr, flash_info_t *info);
  44. static void flash_reset(flash_info_t *info);
  45. static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
  46. static flash_info_t *flash_get_info(ulong base);
  47. /*-----------------------------------------------------------------------
  48. * flash_init()
  49. *
  50. * sets up flash_info and returns size of FLASH (bytes)
  51. */
  52. unsigned long flash_init (void)
  53. {
  54. unsigned long size = 0;
  55. ulong flashbase = CFG_FLASH_BASE;
  56. /* Init: no FLASHes known */
  57. memset(&flash_info[0], 0, sizeof(flash_info_t));
  58. flash_info[0].size =
  59. flash_get_size((FPW *)flashbase, &flash_info[0]);
  60. size = flash_info[0].size;
  61. #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
  62. /* monitor protection ON by default */
  63. flash_protect(FLAG_PROTECT_SET,
  64. CFG_MONITOR_BASE,
  65. CFG_MONITOR_BASE+monitor_flash_len-1,
  66. flash_get_info(CFG_MONITOR_BASE));
  67. #endif
  68. #ifdef CFG_ENV_IS_IN_FLASH
  69. /* ENV protection ON by default */
  70. flash_protect(FLAG_PROTECT_SET,
  71. CFG_ENV_ADDR,
  72. CFG_ENV_ADDR+CFG_ENV_SIZE-1,
  73. flash_get_info(CFG_ENV_ADDR));
  74. #endif
  75. return size ? size : 1;
  76. }
  77. /*-----------------------------------------------------------------------
  78. */
  79. static void flash_reset(flash_info_t *info)
  80. {
  81. FPWV *base = (FPWV *)(info->start[0]);
  82. /* Put FLASH back in read mode */
  83. if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
  84. *base = (FPW)0x00FF00FF; /* Intel Read Mode */
  85. else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
  86. *base = (FPW)0x00F000F0; /* AMD Read Mode */
  87. }
  88. /*-----------------------------------------------------------------------
  89. */
  90. static flash_info_t *flash_get_info(ulong base)
  91. {
  92. int i;
  93. flash_info_t * info;
  94. info = NULL;
  95. for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
  96. info = & flash_info[i];
  97. if (info->size && info->start[0] <= base &&
  98. base <= info->start[0] + info->size - 1)
  99. break;
  100. }
  101. return i == CFG_MAX_FLASH_BANKS ? 0 : info;
  102. }
  103. /*-----------------------------------------------------------------------
  104. */
  105. void flash_print_info (flash_info_t *info)
  106. {
  107. int i;
  108. if (info->flash_id == FLASH_UNKNOWN) {
  109. printf ("missing or unknown FLASH type\n");
  110. return;
  111. }
  112. switch (info->flash_id & FLASH_VENDMASK) {
  113. case FLASH_MAN_AMD: printf ("AMD "); break;
  114. case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
  115. case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
  116. case FLASH_MAN_SST: printf ("SST "); break;
  117. case FLASH_MAN_STM: printf ("STM "); break;
  118. case FLASH_MAN_INTEL: printf ("INTEL "); break;
  119. default: printf ("Unknown Vendor "); break;
  120. }
  121. switch (info->flash_id & FLASH_TYPEMASK) {
  122. case FLASH_S29GL064M:
  123. printf ("S29GL064M-R6 (64Mbit, uniform sector size)\n");
  124. break;
  125. default:
  126. printf ("Unknown Chip Type\n");
  127. break;
  128. }
  129. printf (" Size: %ld MB in %d Sectors\n",
  130. info->size >> 20,
  131. info->sector_count);
  132. printf (" Sector Start Addresses:");
  133. for (i=0; i<info->sector_count; ++i) {
  134. if ((i % 5) == 0) {
  135. printf ("\n ");
  136. }
  137. printf (" %08lX%s",
  138. info->start[i],
  139. info->protect[i] ? " (RO)" : " ");
  140. }
  141. printf ("\n");
  142. return;
  143. }
  144. /*-----------------------------------------------------------------------
  145. */
  146. /*
  147. * The following code cannot be run from FLASH!
  148. */
  149. ulong flash_get_size (FPWV *addr, flash_info_t *info)
  150. {
  151. int i;
  152. ulong base = (ulong)addr;
  153. /* Write auto select command: read Manufacturer ID */
  154. /* Write auto select command sequence and test FLASH answer */
  155. addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
  156. addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */
  157. addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */
  158. /* The manufacturer codes are only 1 byte, so just use 1 byte.
  159. * This works for any bus width and any FLASH device width.
  160. */
  161. udelay(100);
  162. switch (addr[0] & 0xff) {
  163. case (uchar)AMD_MANUFACT:
  164. printf ("Manufacturer: AMD (Spansion)\n");
  165. info->flash_id = FLASH_MAN_AMD;
  166. break;
  167. case (uchar)INTEL_MANUFACT:
  168. printf ("Manufacturer: Intel (not supported yet)\n");
  169. info->flash_id = FLASH_MAN_INTEL;
  170. break;
  171. default:
  172. info->flash_id = FLASH_UNKNOWN;
  173. info->sector_count = 0;
  174. info->size = 0;
  175. break;
  176. }
  177. /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
  178. if (info->flash_id != FLASH_UNKNOWN) switch ((FPW)addr[1]) {
  179. case AMD_ID_MIRROR:
  180. printf ("Mirror Bit flash: addr[14] = %08X addr[15] = %08X\n",
  181. addr[14], addr[15]);
  182. switch(addr[14] & 0xffff) {
  183. case (AMD_ID_GL064M_2 & 0xffff):
  184. if (addr[15] != (AMD_ID_GL064M_3 & 0xffff)) {
  185. printf ("Chip: S29GLxxxM -> unknown\n");
  186. info->flash_id = FLASH_UNKNOWN;
  187. info->sector_count = 0;
  188. info->size = 0;
  189. } else {
  190. printf ("Chip: S29GL064M-R6\n");
  191. info->flash_id += FLASH_S29GL064M;
  192. info->sector_count = 128;
  193. info->size = 0x00800000;
  194. for (i = 0; i < info->sector_count; i++) {
  195. info->start[i] = base;
  196. base += 0x10000;
  197. }
  198. }
  199. break; /* => 16 MB */
  200. default:
  201. printf ("Chip: *** unknown ***\n");
  202. info->flash_id = FLASH_UNKNOWN;
  203. info->sector_count = 0;
  204. info->size = 0;
  205. break;
  206. }
  207. break;
  208. default:
  209. info->flash_id = FLASH_UNKNOWN;
  210. info->sector_count = 0;
  211. info->size = 0;
  212. }
  213. /* Put FLASH back in read mode */
  214. flash_reset(info);
  215. return (info->size);
  216. }
  217. /*-----------------------------------------------------------------------
  218. */
  219. int flash_erase (flash_info_t *info, int s_first, int s_last)
  220. {
  221. FPWV *addr = (FPWV *)(info->start[0]);
  222. int flag, prot, sect, l_sect;
  223. ulong start, now, last;
  224. printf ("flash_erase: first: %d last: %d\n", s_first, s_last);
  225. if ((s_first < 0) || (s_first > s_last)) {
  226. if (info->flash_id == FLASH_UNKNOWN) {
  227. printf ("- missing\n");
  228. } else {
  229. printf ("- no sectors to erase\n");
  230. }
  231. return 1;
  232. }
  233. if ((info->flash_id == FLASH_UNKNOWN) ||
  234. (info->flash_id > FLASH_AMD_COMP)) {
  235. printf ("Can't erase unknown flash type %08lx - aborted\n",
  236. info->flash_id);
  237. return 1;
  238. }
  239. prot = 0;
  240. for (sect=s_first; sect<=s_last; ++sect) {
  241. if (info->protect[sect]) {
  242. prot++;
  243. }
  244. }
  245. if (prot) {
  246. printf ("- Warning: %d protected sectors will not be erased!\n",
  247. prot);
  248. } else {
  249. printf ("\n");
  250. }
  251. l_sect = -1;
  252. /* Disable interrupts which might cause a timeout here */
  253. flag = disable_interrupts();
  254. addr[0x0555] = 0x00AA;
  255. addr[0x02AA] = 0x0055;
  256. addr[0x0555] = 0x0080;
  257. addr[0x0555] = 0x00AA;
  258. addr[0x02AA] = 0x0055;
  259. /* Start erase on unprotected sectors */
  260. for (sect = s_first; sect<=s_last; sect++) {
  261. if (info->protect[sect] == 0) { /* not protected */
  262. addr = (FPWV *)(info->start[sect]);
  263. addr[0] = 0x0030;
  264. l_sect = sect;
  265. }
  266. }
  267. /* re-enable interrupts if necessary */
  268. if (flag)
  269. enable_interrupts();
  270. /* wait at least 80us - let's wait 1 ms */
  271. udelay (1000);
  272. /*
  273. * We wait for the last triggered sector
  274. */
  275. if (l_sect < 0)
  276. goto DONE;
  277. start = get_timer (0);
  278. last = start;
  279. addr = (FPWV *)(info->start[l_sect]);
  280. while ((addr[0] & 0x00000080) != 0x00000080) {
  281. if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
  282. printf ("Timeout\n");
  283. return 1;
  284. }
  285. /* show that we're waiting */
  286. if ((now - last) > 1000) { /* every second */
  287. putc ('.');
  288. last = now;
  289. }
  290. }
  291. DONE:
  292. /* reset to read mode */
  293. addr = (FPWV *)info->start[0];
  294. addr[0] = 0x000000F0; /* reset bank */
  295. printf (" done\n");
  296. return 0;
  297. }
  298. /*-----------------------------------------------------------------------
  299. * Copy memory to flash, returns:
  300. * 0 - OK
  301. * 1 - write timeout
  302. * 2 - Flash not erased
  303. */
  304. int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  305. {
  306. ulong wp, data;
  307. int rc;
  308. if (addr & 1) {
  309. printf ("unaligned destination not supported\n");
  310. return ERR_ALIGN;
  311. };
  312. if ((int) src & 1) {
  313. printf ("unaligned source not supported\n");
  314. return ERR_ALIGN;
  315. };
  316. wp = addr;
  317. while (cnt >= 2) {
  318. data = *((FPWV *)src);
  319. if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
  320. return (rc);
  321. }
  322. src += 2;
  323. wp += 2;
  324. cnt -= 2;
  325. }
  326. if (cnt == 0) {
  327. return (0);
  328. }
  329. if (cnt == 1) {
  330. data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1))
  331. << 8);
  332. if ((rc = write_word_amd(info, (FPW *)wp, data)) != 0) {
  333. return (rc);
  334. }
  335. src += 1;
  336. wp += 1;
  337. cnt -= 1;
  338. }
  339. return ERR_OK;
  340. }
  341. /*-----------------------------------------------------------------------
  342. * Write a word to Flash for AMD FLASH
  343. * A word is 16 or 32 bits, whichever the bus width of the flash bank
  344. * (not an individual chip) is.
  345. *
  346. * returns:
  347. * 0 - OK
  348. * 1 - write timeout
  349. * 2 - Flash not erased
  350. */
  351. static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
  352. {
  353. ulong start;
  354. int flag;
  355. FPWV *base; /* first address in flash bank */
  356. /* Check if Flash is (sufficiently) erased */
  357. if ((*dest & data) != data) {
  358. return (2);
  359. }
  360. base = (FPWV *)(info->start[0]);
  361. /* Disable interrupts which might cause a timeout here */
  362. flag = disable_interrupts();
  363. base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */
  364. base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */
  365. base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */
  366. *dest = data; /* start programming the data */
  367. /* re-enable interrupts if necessary */
  368. if (flag)
  369. enable_interrupts();
  370. start = get_timer (0);
  371. /* data polling for D7 */
  372. while ((*dest & (FPW)0x00000080) != (data & (FPW)0x00000080)) {
  373. if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
  374. *dest = (FPW)0x000000F0; /* reset bank */
  375. return (1);
  376. }
  377. }
  378. return (0);
  379. }