tegra20.dtsi 6.8 KB

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  1. /include/ "skeleton.dtsi"
  2. / {
  3. compatible = "nvidia,tegra20";
  4. interrupt-parent = <&intc>;
  5. host1x {
  6. compatible = "nvidia,tegra20-host1x", "simple-bus";
  7. reg = <0x50000000 0x00024000>;
  8. interrupts = <0 65 0x04 /* mpcore syncpt */
  9. 0 67 0x04>; /* mpcore general */
  10. status = "disabled";
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. ranges = <0x54000000 0x54000000 0x04000000>;
  14. /* video-encoding/decoding */
  15. mpe {
  16. reg = <0x54040000 0x00040000>;
  17. interrupts = <0 68 0x04>;
  18. status = "disabled";
  19. };
  20. /* video input */
  21. vi {
  22. reg = <0x54080000 0x00040000>;
  23. interrupts = <0 69 0x04>;
  24. status = "disabled";
  25. };
  26. /* EPP */
  27. epp {
  28. reg = <0x540c0000 0x00040000>;
  29. interrupts = <0 70 0x04>;
  30. status = "disabled";
  31. };
  32. /* ISP */
  33. isp {
  34. reg = <0x54100000 0x00040000>;
  35. interrupts = <0 71 0x04>;
  36. status = "disabled";
  37. };
  38. /* 2D engine */
  39. gr2d {
  40. reg = <0x54140000 0x00040000>;
  41. interrupts = <0 72 0x04>;
  42. status = "disabled";
  43. };
  44. /* 3D engine */
  45. gr3d {
  46. reg = <0x54180000 0x00040000>;
  47. status = "disabled";
  48. };
  49. /* display controllers */
  50. dc@54200000 {
  51. compatible = "nvidia,tegra20-dc";
  52. reg = <0x54200000 0x00040000>;
  53. interrupts = <0 73 0x04>;
  54. status = "disabled";
  55. rgb {
  56. status = "disabled";
  57. };
  58. };
  59. dc@54240000 {
  60. compatible = "nvidia,tegra20-dc";
  61. reg = <0x54240000 0x00040000>;
  62. interrupts = <0 74 0x04>;
  63. status = "disabled";
  64. rgb {
  65. status = "disabled";
  66. };
  67. };
  68. /* outputs */
  69. hdmi {
  70. compatible = "nvidia,tegra20-hdmi";
  71. reg = <0x54280000 0x00040000>;
  72. interrupts = <0 75 0x04>;
  73. status = "disabled";
  74. };
  75. tvo {
  76. compatible = "nvidia,tegra20-tvo";
  77. reg = <0x542c0000 0x00040000>;
  78. interrupts = <0 76 0x04>;
  79. status = "disabled";
  80. };
  81. dsi {
  82. compatible = "nvidia,tegra20-dsi";
  83. reg = <0x54300000 0x00040000>;
  84. status = "disabled";
  85. };
  86. };
  87. intc: interrupt-controller@50041000 {
  88. compatible = "nvidia,tegra20-gic";
  89. interrupt-controller;
  90. #interrupt-cells = <1>;
  91. reg = < 0x50041000 0x1000 >,
  92. < 0x50040100 0x0100 >;
  93. };
  94. tegra_car: clock@60006000 {
  95. compatible = "nvidia,tegra20-car";
  96. reg = <0x60006000 0x1000>;
  97. #clock-cells = <1>;
  98. };
  99. apbdma: dma {
  100. compatible = "nvidia,tegra20-apbdma";
  101. reg = <0x6000a000 0x1200>;
  102. interrupts = <0 104 0x04
  103. 0 105 0x04
  104. 0 106 0x04
  105. 0 107 0x04
  106. 0 108 0x04
  107. 0 109 0x04
  108. 0 110 0x04
  109. 0 111 0x04
  110. 0 112 0x04
  111. 0 113 0x04
  112. 0 114 0x04
  113. 0 115 0x04
  114. 0 116 0x04
  115. 0 117 0x04
  116. 0 118 0x04
  117. 0 119 0x04>;
  118. };
  119. gpio: gpio@6000d000 {
  120. compatible = "nvidia,tegra20-gpio";
  121. reg = < 0x6000d000 0x1000 >;
  122. interrupts = < 64 65 66 67 87 119 121 >;
  123. #gpio-cells = <2>;
  124. gpio-controller;
  125. };
  126. pinmux: pinmux@70000000 {
  127. compatible = "nvidia,tegra20-pinmux";
  128. reg = < 0x70000014 0x10 /* Tri-state registers */
  129. 0x70000080 0x20 /* Mux registers */
  130. 0x700000a0 0x14 /* Pull-up/down registers */
  131. 0x70000868 0xa8 >; /* Pad control registers */
  132. };
  133. das@70000c00 {
  134. #address-cells = <1>;
  135. #size-cells = <0>;
  136. compatible = "nvidia,tegra20-das";
  137. reg = <0x70000c00 0x80>;
  138. };
  139. i2s@70002800 {
  140. #address-cells = <1>;
  141. #size-cells = <0>;
  142. compatible = "nvidia,tegra20-i2s";
  143. reg = <0x70002800 0x200>;
  144. interrupts = < 45 >;
  145. dma-channel = < 2 >;
  146. };
  147. i2s@70002a00 {
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. compatible = "nvidia,tegra20-i2s";
  151. reg = <0x70002a00 0x200>;
  152. interrupts = < 35 >;
  153. dma-channel = < 1 >;
  154. };
  155. serial@70006000 {
  156. compatible = "nvidia,tegra20-uart";
  157. reg = <0x70006000 0x40>;
  158. reg-shift = <2>;
  159. interrupts = < 68 >;
  160. };
  161. serial@70006040 {
  162. compatible = "nvidia,tegra20-uart";
  163. reg = <0x70006040 0x40>;
  164. reg-shift = <2>;
  165. interrupts = < 69 >;
  166. };
  167. serial@70006200 {
  168. compatible = "nvidia,tegra20-uart";
  169. reg = <0x70006200 0x100>;
  170. reg-shift = <2>;
  171. interrupts = < 78 >;
  172. };
  173. serial@70006300 {
  174. compatible = "nvidia,tegra20-uart";
  175. reg = <0x70006300 0x100>;
  176. reg-shift = <2>;
  177. interrupts = < 122 >;
  178. };
  179. serial@70006400 {
  180. compatible = "nvidia,tegra20-uart";
  181. reg = <0x70006400 0x100>;
  182. reg-shift = <2>;
  183. interrupts = < 123 >;
  184. };
  185. nand: nand-controller@70008000 {
  186. #address-cells = <1>;
  187. #size-cells = <0>;
  188. compatible = "nvidia,tegra20-nand";
  189. reg = <0x70008000 0x100>;
  190. };
  191. pwm: pwm@7000a000 {
  192. compatible = "nvidia,tegra20-pwm";
  193. reg = <0x7000a000 0x100>;
  194. #pwm-cells = <2>;
  195. };
  196. i2c@7000c000 {
  197. #address-cells = <1>;
  198. #size-cells = <0>;
  199. compatible = "nvidia,tegra20-i2c";
  200. reg = <0x7000C000 0x100>;
  201. interrupts = < 70 >;
  202. /* PERIPH_ID_I2C1, PLL_P_OUT3 */
  203. clocks = <&tegra_car 12>, <&tegra_car 124>;
  204. };
  205. spi@7000c380 {
  206. compatible = "nvidia,tegra20-sflash";
  207. reg = <0x7000c380 0x80>;
  208. interrupts = <0 39 0x04>;
  209. nvidia,dma-request-selector = <&apbdma 11>;
  210. #address-cells = <1>;
  211. #size-cells = <0>;
  212. status = "disabled";
  213. /* PERIPH_ID_SPI1, PLLP_OUT0 */
  214. clocks = <&tegra_car 43>;
  215. };
  216. i2c@7000c400 {
  217. #address-cells = <1>;
  218. #size-cells = <0>;
  219. compatible = "nvidia,tegra20-i2c";
  220. reg = <0x7000C400 0x100>;
  221. interrupts = < 116 >;
  222. /* PERIPH_ID_I2C2, PLL_P_OUT3 */
  223. clocks = <&tegra_car 54>, <&tegra_car 124>;
  224. };
  225. i2c@7000c500 {
  226. #address-cells = <1>;
  227. #size-cells = <0>;
  228. compatible = "nvidia,tegra20-i2c";
  229. reg = <0x7000C500 0x100>;
  230. interrupts = < 124 >;
  231. /* PERIPH_ID_I2C3, PLL_P_OUT3 */
  232. clocks = <&tegra_car 67>, <&tegra_car 124>;
  233. };
  234. i2c@7000d000 {
  235. #address-cells = <1>;
  236. #size-cells = <0>;
  237. compatible = "nvidia,tegra20-i2c-dvc";
  238. reg = <0x7000D000 0x200>;
  239. interrupts = < 85 >;
  240. /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
  241. clocks = <&tegra_car 47>, <&tegra_car 124>;
  242. };
  243. kbc@7000e200 {
  244. compatible = "nvidia,tegra20-kbc";
  245. reg = <0x7000e200 0x0078>;
  246. };
  247. emc@7000f400 {
  248. #address-cells = < 1 >;
  249. #size-cells = < 0 >;
  250. compatible = "nvidia,tegra20-emc";
  251. reg = <0x7000f400 0x200>;
  252. };
  253. usb@c5000000 {
  254. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  255. reg = <0xc5000000 0x4000>;
  256. interrupts = < 52 >;
  257. phy_type = "utmi";
  258. clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
  259. nvidia,has-legacy-mode;
  260. };
  261. usb@c5004000 {
  262. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  263. reg = <0xc5004000 0x4000>;
  264. interrupts = < 53 >;
  265. phy_type = "ulpi";
  266. clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
  267. };
  268. usb@c5008000 {
  269. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  270. reg = <0xc5008000 0x4000>;
  271. interrupts = < 129 >;
  272. phy_type = "utmi";
  273. clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
  274. };
  275. sdhci@c8000000 {
  276. compatible = "nvidia,tegra20-sdhci";
  277. reg = <0xc8000000 0x200>;
  278. interrupts = < 46 >;
  279. };
  280. sdhci@c8000200 {
  281. compatible = "nvidia,tegra20-sdhci";
  282. reg = <0xc8000200 0x200>;
  283. interrupts = < 47 >;
  284. };
  285. sdhci@c8000400 {
  286. compatible = "nvidia,tegra20-sdhci";
  287. reg = <0xc8000400 0x200>;
  288. interrupts = < 51 >;
  289. };
  290. sdhci@c8000600 {
  291. compatible = "nvidia,tegra20-sdhci";
  292. reg = <0xc8000600 0x200>;
  293. interrupts = < 63 >;
  294. };
  295. };