ehci-hcd.c 22 KB

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  1. /*-
  2. * Copyright (c) 2007-2008, Juniper Networks, Inc.
  3. * Copyright (c) 2008, Excito Elektronik i Skåne AB
  4. * Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
  5. *
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2 of
  11. * the License.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/byteorder.h>
  25. #include <usb.h>
  26. #include <asm/io.h>
  27. #include <malloc.h>
  28. #include <watchdog.h>
  29. #include "ehci.h"
  30. int rootdev;
  31. struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
  32. volatile struct ehci_hcor *hcor;
  33. static uint16_t portreset;
  34. static struct QH qh_list __attribute__((aligned(32)));
  35. static struct descriptor {
  36. struct usb_hub_descriptor hub;
  37. struct usb_device_descriptor device;
  38. struct usb_linux_config_descriptor config;
  39. struct usb_linux_interface_descriptor interface;
  40. struct usb_endpoint_descriptor endpoint;
  41. } __attribute__ ((packed)) descriptor = {
  42. {
  43. 0x8, /* bDescLength */
  44. 0x29, /* bDescriptorType: hub descriptor */
  45. 2, /* bNrPorts -- runtime modified */
  46. 0, /* wHubCharacteristics */
  47. 10, /* bPwrOn2PwrGood */
  48. 0, /* bHubCntrCurrent */
  49. {}, /* Device removable */
  50. {} /* at most 7 ports! XXX */
  51. },
  52. {
  53. 0x12, /* bLength */
  54. 1, /* bDescriptorType: UDESC_DEVICE */
  55. cpu_to_le16(0x0200), /* bcdUSB: v2.0 */
  56. 9, /* bDeviceClass: UDCLASS_HUB */
  57. 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
  58. 1, /* bDeviceProtocol: UDPROTO_HSHUBSTT */
  59. 64, /* bMaxPacketSize: 64 bytes */
  60. 0x0000, /* idVendor */
  61. 0x0000, /* idProduct */
  62. cpu_to_le16(0x0100), /* bcdDevice */
  63. 1, /* iManufacturer */
  64. 2, /* iProduct */
  65. 0, /* iSerialNumber */
  66. 1 /* bNumConfigurations: 1 */
  67. },
  68. {
  69. 0x9,
  70. 2, /* bDescriptorType: UDESC_CONFIG */
  71. cpu_to_le16(0x19),
  72. 1, /* bNumInterface */
  73. 1, /* bConfigurationValue */
  74. 0, /* iConfiguration */
  75. 0x40, /* bmAttributes: UC_SELF_POWER */
  76. 0 /* bMaxPower */
  77. },
  78. {
  79. 0x9, /* bLength */
  80. 4, /* bDescriptorType: UDESC_INTERFACE */
  81. 0, /* bInterfaceNumber */
  82. 0, /* bAlternateSetting */
  83. 1, /* bNumEndpoints */
  84. 9, /* bInterfaceClass: UICLASS_HUB */
  85. 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
  86. 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  87. 0 /* iInterface */
  88. },
  89. {
  90. 0x7, /* bLength */
  91. 5, /* bDescriptorType: UDESC_ENDPOINT */
  92. 0x81, /* bEndpointAddress:
  93. * UE_DIR_IN | EHCI_INTR_ENDPT
  94. */
  95. 3, /* bmAttributes: UE_INTERRUPT */
  96. 8, /* wMaxPacketSize */
  97. 255 /* bInterval */
  98. },
  99. };
  100. #if defined(CONFIG_EHCI_IS_TDI)
  101. #define ehci_is_TDI() (1)
  102. #else
  103. #define ehci_is_TDI() (0)
  104. #endif
  105. #if defined(CONFIG_EHCI_DCACHE)
  106. /*
  107. * Routines to handle (flush/invalidate) the dcache for the QH and qTD
  108. * structures and data buffers. This is needed on platforms using this
  109. * EHCI support with dcache enabled.
  110. */
  111. static void flush_invalidate(u32 addr, int size, int flush)
  112. {
  113. if (flush)
  114. flush_dcache_range(addr, addr + size);
  115. else
  116. invalidate_dcache_range(addr, addr + size);
  117. }
  118. static void cache_qtd(struct qTD *qtd, int flush)
  119. {
  120. u32 *ptr = (u32 *)qtd->qt_buffer[0];
  121. int len = (qtd->qt_token & 0x7fff0000) >> 16;
  122. flush_invalidate((u32)qtd, sizeof(struct qTD), flush);
  123. if (ptr && len)
  124. flush_invalidate((u32)ptr, len, flush);
  125. }
  126. static inline struct QH *qh_addr(struct QH *qh)
  127. {
  128. return (struct QH *)((u32)qh & 0xffffffe0);
  129. }
  130. static void cache_qh(struct QH *qh, int flush)
  131. {
  132. struct qTD *qtd;
  133. struct qTD *next;
  134. static struct qTD *first_qtd;
  135. /*
  136. * Walk the QH list and flush/invalidate all entries
  137. */
  138. while (1) {
  139. flush_invalidate((u32)qh_addr(qh), sizeof(struct QH), flush);
  140. if ((u32)qh & QH_LINK_TYPE_QH)
  141. break;
  142. qh = qh_addr(qh);
  143. qh = (struct QH *)qh->qh_link;
  144. }
  145. qh = qh_addr(qh);
  146. /*
  147. * Save first qTD pointer, needed for invalidating pass on this QH
  148. */
  149. if (flush)
  150. first_qtd = qtd = (struct qTD *)(*(u32 *)&qh->qh_overlay &
  151. 0xffffffe0);
  152. else
  153. qtd = first_qtd;
  154. /*
  155. * Walk the qTD list and flush/invalidate all entries
  156. */
  157. while (1) {
  158. if (qtd == NULL)
  159. break;
  160. cache_qtd(qtd, flush);
  161. next = (struct qTD *)((u32)qtd->qt_next & 0xffffffe0);
  162. if (next == qtd)
  163. break;
  164. qtd = next;
  165. }
  166. }
  167. static inline void ehci_flush_dcache(struct QH *qh)
  168. {
  169. cache_qh(qh, 1);
  170. }
  171. static inline void ehci_invalidate_dcache(struct QH *qh)
  172. {
  173. cache_qh(qh, 0);
  174. }
  175. #else /* CONFIG_EHCI_DCACHE */
  176. /*
  177. *
  178. */
  179. static inline void ehci_flush_dcache(struct QH *qh)
  180. {
  181. }
  182. static inline void ehci_invalidate_dcache(struct QH *qh)
  183. {
  184. }
  185. #endif /* CONFIG_EHCI_DCACHE */
  186. void __ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
  187. {
  188. mdelay(50);
  189. }
  190. void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
  191. __attribute__((weak, alias("__ehci_powerup_fixup")));
  192. static int handshake(uint32_t *ptr, uint32_t mask, uint32_t done, int usec)
  193. {
  194. uint32_t result;
  195. do {
  196. result = ehci_readl(ptr);
  197. udelay(5);
  198. if (result == ~(uint32_t)0)
  199. return -1;
  200. result &= mask;
  201. if (result == done)
  202. return 0;
  203. usec--;
  204. } while (usec > 0);
  205. return -1;
  206. }
  207. static void ehci_free(void *p, size_t sz)
  208. {
  209. }
  210. static int ehci_reset(void)
  211. {
  212. uint32_t cmd;
  213. uint32_t tmp;
  214. uint32_t *reg_ptr;
  215. int ret = 0;
  216. cmd = ehci_readl(&hcor->or_usbcmd);
  217. cmd = (cmd & ~CMD_RUN) | CMD_RESET;
  218. ehci_writel(&hcor->or_usbcmd, cmd);
  219. ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
  220. if (ret < 0) {
  221. printf("EHCI fail to reset\n");
  222. goto out;
  223. }
  224. if (ehci_is_TDI()) {
  225. reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
  226. tmp = ehci_readl(reg_ptr);
  227. tmp |= USBMODE_CM_HC;
  228. #if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
  229. tmp |= USBMODE_BE;
  230. #endif
  231. ehci_writel(reg_ptr, tmp);
  232. }
  233. #ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
  234. cmd = ehci_readl(&hcor->or_txfilltuning);
  235. cmd &= ~TXFIFO_THRESH(0x3f);
  236. cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
  237. ehci_writel(&hcor->or_txfilltuning, cmd);
  238. #endif
  239. out:
  240. return ret;
  241. }
  242. static void *ehci_alloc(size_t sz, size_t align)
  243. {
  244. static struct QH qh __attribute__((aligned(32)));
  245. static struct qTD td[3] __attribute__((aligned (32)));
  246. static int ntds;
  247. void *p;
  248. switch (sz) {
  249. case sizeof(struct QH):
  250. p = &qh;
  251. ntds = 0;
  252. break;
  253. case sizeof(struct qTD):
  254. if (ntds == 3) {
  255. debug("out of TDs\n");
  256. return NULL;
  257. }
  258. p = &td[ntds];
  259. ntds++;
  260. break;
  261. default:
  262. debug("unknown allocation size\n");
  263. return NULL;
  264. }
  265. memset(p, 0, sz);
  266. return p;
  267. }
  268. static int ehci_td_buffer(struct qTD *td, void *buf, size_t sz)
  269. {
  270. uint32_t addr, delta, next;
  271. int idx;
  272. addr = (uint32_t) buf;
  273. idx = 0;
  274. while (idx < 5) {
  275. td->qt_buffer[idx] = cpu_to_hc32(addr);
  276. td->qt_buffer_hi[idx] = 0;
  277. next = (addr + 4096) & ~4095;
  278. delta = next - addr;
  279. if (delta >= sz)
  280. break;
  281. sz -= delta;
  282. addr = next;
  283. idx++;
  284. }
  285. if (idx == 5) {
  286. debug("out of buffer pointers (%u bytes left)\n", sz);
  287. return -1;
  288. }
  289. return 0;
  290. }
  291. static int
  292. ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
  293. int length, struct devrequest *req)
  294. {
  295. struct QH *qh;
  296. struct qTD *td;
  297. volatile struct qTD *vtd;
  298. unsigned long ts;
  299. uint32_t *tdp;
  300. uint32_t endpt, token, usbsts;
  301. uint32_t c, toggle;
  302. uint32_t cmd;
  303. int timeout;
  304. int ret = 0;
  305. debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
  306. buffer, length, req);
  307. if (req != NULL)
  308. debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n",
  309. req->request, req->request,
  310. req->requesttype, req->requesttype,
  311. le16_to_cpu(req->value), le16_to_cpu(req->value),
  312. le16_to_cpu(req->index));
  313. qh = ehci_alloc(sizeof(struct QH), 32);
  314. if (qh == NULL) {
  315. debug("unable to allocate QH\n");
  316. return -1;
  317. }
  318. qh->qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
  319. c = (usb_pipespeed(pipe) != USB_SPEED_HIGH &&
  320. usb_pipeendpoint(pipe) == 0) ? 1 : 0;
  321. endpt = (8 << 28) |
  322. (c << 27) |
  323. (usb_maxpacket(dev, pipe) << 16) |
  324. (0 << 15) |
  325. (1 << 14) |
  326. (usb_pipespeed(pipe) << 12) |
  327. (usb_pipeendpoint(pipe) << 8) |
  328. (0 << 7) | (usb_pipedevice(pipe) << 0);
  329. qh->qh_endpt1 = cpu_to_hc32(endpt);
  330. endpt = (1 << 30) |
  331. (dev->portnr << 23) |
  332. (dev->parent->devnum << 16) | (0 << 8) | (0 << 0);
  333. qh->qh_endpt2 = cpu_to_hc32(endpt);
  334. qh->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  335. td = NULL;
  336. tdp = &qh->qh_overlay.qt_next;
  337. toggle =
  338. usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
  339. if (req != NULL) {
  340. td = ehci_alloc(sizeof(struct qTD), 32);
  341. if (td == NULL) {
  342. debug("unable to allocate SETUP td\n");
  343. goto fail;
  344. }
  345. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  346. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  347. token = (0 << 31) |
  348. (sizeof(*req) << 16) |
  349. (0 << 15) | (0 << 12) | (3 << 10) | (2 << 8) | (0x80 << 0);
  350. td->qt_token = cpu_to_hc32(token);
  351. if (ehci_td_buffer(td, req, sizeof(*req)) != 0) {
  352. debug("unable construct SETUP td\n");
  353. ehci_free(td, sizeof(*td));
  354. goto fail;
  355. }
  356. *tdp = cpu_to_hc32((uint32_t) td);
  357. tdp = &td->qt_next;
  358. toggle = 1;
  359. }
  360. if (length > 0 || req == NULL) {
  361. td = ehci_alloc(sizeof(struct qTD), 32);
  362. if (td == NULL) {
  363. debug("unable to allocate DATA td\n");
  364. goto fail;
  365. }
  366. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  367. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  368. token = (toggle << 31) |
  369. (length << 16) |
  370. ((req == NULL ? 1 : 0) << 15) |
  371. (0 << 12) |
  372. (3 << 10) |
  373. ((usb_pipein(pipe) ? 1 : 0) << 8) | (0x80 << 0);
  374. td->qt_token = cpu_to_hc32(token);
  375. if (ehci_td_buffer(td, buffer, length) != 0) {
  376. debug("unable construct DATA td\n");
  377. ehci_free(td, sizeof(*td));
  378. goto fail;
  379. }
  380. *tdp = cpu_to_hc32((uint32_t) td);
  381. tdp = &td->qt_next;
  382. }
  383. if (req != NULL) {
  384. td = ehci_alloc(sizeof(struct qTD), 32);
  385. if (td == NULL) {
  386. debug("unable to allocate ACK td\n");
  387. goto fail;
  388. }
  389. td->qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  390. td->qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  391. token = (toggle << 31) |
  392. (0 << 16) |
  393. (1 << 15) |
  394. (0 << 12) |
  395. (3 << 10) |
  396. ((usb_pipein(pipe) ? 0 : 1) << 8) | (0x80 << 0);
  397. td->qt_token = cpu_to_hc32(token);
  398. *tdp = cpu_to_hc32((uint32_t) td);
  399. tdp = &td->qt_next;
  400. }
  401. qh_list.qh_link = cpu_to_hc32((uint32_t) qh | QH_LINK_TYPE_QH);
  402. /* Flush dcache */
  403. ehci_flush_dcache(&qh_list);
  404. usbsts = ehci_readl(&hcor->or_usbsts);
  405. ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
  406. /* Enable async. schedule. */
  407. cmd = ehci_readl(&hcor->or_usbcmd);
  408. cmd |= CMD_ASE;
  409. ehci_writel(&hcor->or_usbcmd, cmd);
  410. ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, STD_ASS,
  411. 100 * 1000);
  412. if (ret < 0) {
  413. printf("EHCI fail timeout STD_ASS set\n");
  414. goto fail;
  415. }
  416. /* Wait for TDs to be processed. */
  417. ts = get_timer(0);
  418. vtd = td;
  419. timeout = USB_TIMEOUT_MS(pipe);
  420. do {
  421. /* Invalidate dcache */
  422. ehci_invalidate_dcache(&qh_list);
  423. token = hc32_to_cpu(vtd->qt_token);
  424. if (!(token & 0x80))
  425. break;
  426. WATCHDOG_RESET();
  427. } while (get_timer(ts) < timeout);
  428. /* Check that the TD processing happened */
  429. if (token & 0x80) {
  430. printf("EHCI timed out on TD - token=%#x\n", token);
  431. }
  432. /* Disable async schedule. */
  433. cmd = ehci_readl(&hcor->or_usbcmd);
  434. cmd &= ~CMD_ASE;
  435. ehci_writel(&hcor->or_usbcmd, cmd);
  436. ret = handshake((uint32_t *)&hcor->or_usbsts, STD_ASS, 0,
  437. 100 * 1000);
  438. if (ret < 0) {
  439. printf("EHCI fail timeout STD_ASS reset\n");
  440. goto fail;
  441. }
  442. qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
  443. token = hc32_to_cpu(qh->qh_overlay.qt_token);
  444. if (!(token & 0x80)) {
  445. debug("TOKEN=%#x\n", token);
  446. switch (token & 0xfc) {
  447. case 0:
  448. toggle = token >> 31;
  449. usb_settoggle(dev, usb_pipeendpoint(pipe),
  450. usb_pipeout(pipe), toggle);
  451. dev->status = 0;
  452. break;
  453. case 0x40:
  454. dev->status = USB_ST_STALLED;
  455. break;
  456. case 0xa0:
  457. case 0x20:
  458. dev->status = USB_ST_BUF_ERR;
  459. break;
  460. case 0x50:
  461. case 0x10:
  462. dev->status = USB_ST_BABBLE_DET;
  463. break;
  464. default:
  465. dev->status = USB_ST_CRC_ERR;
  466. if ((token & 0x40) == 0x40)
  467. dev->status |= USB_ST_STALLED;
  468. break;
  469. }
  470. dev->act_len = length - ((token >> 16) & 0x7fff);
  471. } else {
  472. dev->act_len = 0;
  473. debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
  474. dev->devnum, ehci_readl(&hcor->or_usbsts),
  475. ehci_readl(&hcor->or_portsc[0]),
  476. ehci_readl(&hcor->or_portsc[1]));
  477. }
  478. return (dev->status != USB_ST_NOT_PROC) ? 0 : -1;
  479. fail:
  480. td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
  481. while (td != (void *)QT_NEXT_TERMINATE) {
  482. qh->qh_overlay.qt_next = td->qt_next;
  483. ehci_free(td, sizeof(*td));
  484. td = (void *)hc32_to_cpu(qh->qh_overlay.qt_next);
  485. }
  486. ehci_free(qh, sizeof(*qh));
  487. return -1;
  488. }
  489. static inline int min3(int a, int b, int c)
  490. {
  491. if (b < a)
  492. a = b;
  493. if (c < a)
  494. a = c;
  495. return a;
  496. }
  497. int
  498. ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
  499. int length, struct devrequest *req)
  500. {
  501. uint8_t tmpbuf[4];
  502. u16 typeReq;
  503. void *srcptr = NULL;
  504. int len, srclen;
  505. uint32_t reg;
  506. uint32_t *status_reg;
  507. if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
  508. printf("The request port(%d) is not configured\n",
  509. le16_to_cpu(req->index) - 1);
  510. return -1;
  511. }
  512. status_reg = (uint32_t *)&hcor->or_portsc[
  513. le16_to_cpu(req->index) - 1];
  514. srclen = 0;
  515. debug("req=%u (%#x), type=%u (%#x), value=%u, index=%u\n",
  516. req->request, req->request,
  517. req->requesttype, req->requesttype,
  518. le16_to_cpu(req->value), le16_to_cpu(req->index));
  519. typeReq = req->request | req->requesttype << 8;
  520. switch (typeReq) {
  521. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  522. switch (le16_to_cpu(req->value) >> 8) {
  523. case USB_DT_DEVICE:
  524. debug("USB_DT_DEVICE request\n");
  525. srcptr = &descriptor.device;
  526. srclen = 0x12;
  527. break;
  528. case USB_DT_CONFIG:
  529. debug("USB_DT_CONFIG config\n");
  530. srcptr = &descriptor.config;
  531. srclen = 0x19;
  532. break;
  533. case USB_DT_STRING:
  534. debug("USB_DT_STRING config\n");
  535. switch (le16_to_cpu(req->value) & 0xff) {
  536. case 0: /* Language */
  537. srcptr = "\4\3\1\0";
  538. srclen = 4;
  539. break;
  540. case 1: /* Vendor */
  541. srcptr = "\16\3u\0-\0b\0o\0o\0t\0";
  542. srclen = 14;
  543. break;
  544. case 2: /* Product */
  545. srcptr = "\52\3E\0H\0C\0I\0 "
  546. "\0H\0o\0s\0t\0 "
  547. "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
  548. srclen = 42;
  549. break;
  550. default:
  551. debug("unknown value DT_STRING %x\n",
  552. le16_to_cpu(req->value));
  553. goto unknown;
  554. }
  555. break;
  556. default:
  557. debug("unknown value %x\n", le16_to_cpu(req->value));
  558. goto unknown;
  559. }
  560. break;
  561. case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
  562. switch (le16_to_cpu(req->value) >> 8) {
  563. case USB_DT_HUB:
  564. debug("USB_DT_HUB config\n");
  565. srcptr = &descriptor.hub;
  566. srclen = 0x8;
  567. break;
  568. default:
  569. debug("unknown value %x\n", le16_to_cpu(req->value));
  570. goto unknown;
  571. }
  572. break;
  573. case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
  574. debug("USB_REQ_SET_ADDRESS\n");
  575. rootdev = le16_to_cpu(req->value);
  576. break;
  577. case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
  578. debug("USB_REQ_SET_CONFIGURATION\n");
  579. /* Nothing to do */
  580. break;
  581. case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
  582. tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
  583. tmpbuf[1] = 0;
  584. srcptr = tmpbuf;
  585. srclen = 2;
  586. break;
  587. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  588. memset(tmpbuf, 0, 4);
  589. reg = ehci_readl(status_reg);
  590. if (reg & EHCI_PS_CS)
  591. tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
  592. if (reg & EHCI_PS_PE)
  593. tmpbuf[0] |= USB_PORT_STAT_ENABLE;
  594. if (reg & EHCI_PS_SUSP)
  595. tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
  596. if (reg & EHCI_PS_OCA)
  597. tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
  598. if (reg & EHCI_PS_PR)
  599. tmpbuf[0] |= USB_PORT_STAT_RESET;
  600. if (reg & EHCI_PS_PP)
  601. tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
  602. if (ehci_is_TDI()) {
  603. switch ((reg >> 26) & 3) {
  604. case 0:
  605. break;
  606. case 1:
  607. tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
  608. break;
  609. case 2:
  610. default:
  611. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  612. break;
  613. }
  614. } else {
  615. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  616. }
  617. if (reg & EHCI_PS_CSC)
  618. tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
  619. if (reg & EHCI_PS_PEC)
  620. tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
  621. if (reg & EHCI_PS_OCC)
  622. tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
  623. if (portreset & (1 << le16_to_cpu(req->index)))
  624. tmpbuf[2] |= USB_PORT_STAT_C_RESET;
  625. srcptr = tmpbuf;
  626. srclen = 4;
  627. break;
  628. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  629. reg = ehci_readl(status_reg);
  630. reg &= ~EHCI_PS_CLEAR;
  631. switch (le16_to_cpu(req->value)) {
  632. case USB_PORT_FEAT_ENABLE:
  633. reg |= EHCI_PS_PE;
  634. ehci_writel(status_reg, reg);
  635. break;
  636. case USB_PORT_FEAT_POWER:
  637. if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
  638. reg |= EHCI_PS_PP;
  639. ehci_writel(status_reg, reg);
  640. }
  641. break;
  642. case USB_PORT_FEAT_RESET:
  643. if ((reg & (EHCI_PS_PE | EHCI_PS_CS)) == EHCI_PS_CS &&
  644. !ehci_is_TDI() &&
  645. EHCI_PS_IS_LOWSPEED(reg)) {
  646. /* Low speed device, give up ownership. */
  647. debug("port %d low speed --> companion\n",
  648. req->index - 1);
  649. reg |= EHCI_PS_PO;
  650. ehci_writel(status_reg, reg);
  651. break;
  652. } else {
  653. int ret;
  654. reg |= EHCI_PS_PR;
  655. reg &= ~EHCI_PS_PE;
  656. ehci_writel(status_reg, reg);
  657. /*
  658. * caller must wait, then call GetPortStatus
  659. * usb 2.0 specification say 50 ms resets on
  660. * root
  661. */
  662. ehci_powerup_fixup(status_reg, &reg);
  663. ehci_writel(status_reg, reg & ~EHCI_PS_PR);
  664. /*
  665. * A host controller must terminate the reset
  666. * and stabilize the state of the port within
  667. * 2 milliseconds
  668. */
  669. ret = handshake(status_reg, EHCI_PS_PR, 0,
  670. 2 * 1000);
  671. if (!ret)
  672. portreset |=
  673. 1 << le16_to_cpu(req->index);
  674. else
  675. printf("port(%d) reset error\n",
  676. le16_to_cpu(req->index) - 1);
  677. }
  678. break;
  679. default:
  680. debug("unknown feature %x\n", le16_to_cpu(req->value));
  681. goto unknown;
  682. }
  683. /* unblock posted writes */
  684. (void) ehci_readl(&hcor->or_usbcmd);
  685. break;
  686. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  687. reg = ehci_readl(status_reg);
  688. switch (le16_to_cpu(req->value)) {
  689. case USB_PORT_FEAT_ENABLE:
  690. reg &= ~EHCI_PS_PE;
  691. break;
  692. case USB_PORT_FEAT_C_ENABLE:
  693. reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
  694. break;
  695. case USB_PORT_FEAT_POWER:
  696. if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
  697. reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
  698. case USB_PORT_FEAT_C_CONNECTION:
  699. reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
  700. break;
  701. case USB_PORT_FEAT_OVER_CURRENT:
  702. reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
  703. break;
  704. case USB_PORT_FEAT_C_RESET:
  705. portreset &= ~(1 << le16_to_cpu(req->index));
  706. break;
  707. default:
  708. debug("unknown feature %x\n", le16_to_cpu(req->value));
  709. goto unknown;
  710. }
  711. ehci_writel(status_reg, reg);
  712. /* unblock posted write */
  713. (void) ehci_readl(&hcor->or_usbcmd);
  714. break;
  715. default:
  716. debug("Unknown request\n");
  717. goto unknown;
  718. }
  719. mdelay(1);
  720. len = min3(srclen, le16_to_cpu(req->length), length);
  721. if (srcptr != NULL && len > 0)
  722. memcpy(buffer, srcptr, len);
  723. else
  724. debug("Len is 0\n");
  725. dev->act_len = len;
  726. dev->status = 0;
  727. return 0;
  728. unknown:
  729. debug("requesttype=%x, request=%x, value=%x, index=%x, length=%x\n",
  730. req->requesttype, req->request, le16_to_cpu(req->value),
  731. le16_to_cpu(req->index), le16_to_cpu(req->length));
  732. dev->act_len = 0;
  733. dev->status = USB_ST_STALLED;
  734. return -1;
  735. }
  736. int usb_lowlevel_stop(void)
  737. {
  738. return ehci_hcd_stop();
  739. }
  740. int usb_lowlevel_init(void)
  741. {
  742. uint32_t reg;
  743. uint32_t cmd;
  744. if (ehci_hcd_init() != 0)
  745. return -1;
  746. /* EHCI spec section 4.1 */
  747. if (ehci_reset() != 0)
  748. return -1;
  749. #if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
  750. if (ehci_hcd_init() != 0)
  751. return -1;
  752. #endif
  753. /* Set head of reclaim list */
  754. memset(&qh_list, 0, sizeof(qh_list));
  755. qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH);
  756. qh_list.qh_endpt1 = cpu_to_hc32((1 << 15) | (USB_SPEED_HIGH << 12));
  757. qh_list.qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
  758. qh_list.qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
  759. qh_list.qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
  760. qh_list.qh_overlay.qt_token = cpu_to_hc32(0x40);
  761. /* Set async. queue head pointer. */
  762. ehci_writel(&hcor->or_asynclistaddr, (uint32_t)&qh_list);
  763. reg = ehci_readl(&hccr->cr_hcsparams);
  764. descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
  765. printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
  766. /* Port Indicators */
  767. if (HCS_INDICATOR(reg))
  768. descriptor.hub.wHubCharacteristics |= 0x80;
  769. /* Port Power Control */
  770. if (HCS_PPC(reg))
  771. descriptor.hub.wHubCharacteristics |= 0x01;
  772. /* Start the host controller. */
  773. cmd = ehci_readl(&hcor->or_usbcmd);
  774. /*
  775. * Philips, Intel, and maybe others need CMD_RUN before the
  776. * root hub will detect new devices (why?); NEC doesn't
  777. */
  778. cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
  779. cmd |= CMD_RUN;
  780. ehci_writel(&hcor->or_usbcmd, cmd);
  781. /* take control over the ports */
  782. cmd = ehci_readl(&hcor->or_configflag);
  783. cmd |= FLAG_CF;
  784. ehci_writel(&hcor->or_configflag, cmd);
  785. /* unblock posted write */
  786. cmd = ehci_readl(&hcor->or_usbcmd);
  787. mdelay(5);
  788. reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
  789. printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
  790. rootdev = 0;
  791. return 0;
  792. }
  793. int
  794. submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  795. int length)
  796. {
  797. if (usb_pipetype(pipe) != PIPE_BULK) {
  798. debug("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
  799. return -1;
  800. }
  801. return ehci_submit_async(dev, pipe, buffer, length, NULL);
  802. }
  803. int
  804. submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  805. int length, struct devrequest *setup)
  806. {
  807. if (usb_pipetype(pipe) != PIPE_CONTROL) {
  808. debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
  809. return -1;
  810. }
  811. if (usb_pipedevice(pipe) == rootdev) {
  812. if (rootdev == 0)
  813. dev->speed = USB_SPEED_HIGH;
  814. return ehci_submit_root(dev, pipe, buffer, length, setup);
  815. }
  816. return ehci_submit_async(dev, pipe, buffer, length, setup);
  817. }
  818. int
  819. submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  820. int length, int interval)
  821. {
  822. debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d",
  823. dev, pipe, buffer, length, interval);
  824. return ehci_submit_async(dev, pipe, buffer, length, NULL);
  825. }