exbitgen.c 4.0 KB

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  1. #include <asm/u-boot.h>
  2. #include <asm/processor.h>
  3. #include <common.h>
  4. #include "exbitgen.h"
  5. void sdram_init(void);
  6. /* ************************************************************************ */
  7. int board_early_init_f (void)
  8. /* ------------------------------------------------------------------------ --
  9. * Purpose :
  10. * Remarks :
  11. * Restrictions:
  12. * See also :
  13. * Example :
  14. * ************************************************************************ */
  15. {
  16. unsigned long i;
  17. /*-------------------------------------------------------------------------+
  18. | Interrupt controller setup for the Walnut board.
  19. | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
  20. | IRQ 16 405GP internally generated; active low; level sensitive
  21. | IRQ 17-24 RESERVED
  22. | IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
  23. | IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
  24. | IRQ 27 (EXT IRQ 2) Not Used
  25. | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  26. | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  27. | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  28. | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  29. | Note for Walnut board:
  30. | An interrupt taken for the FPGA (IRQ 25) indicates that either
  31. | the Mouse, Keyboard, IRDA, or External Expansion caused the
  32. | interrupt. The FPGA must be read to determine which device
  33. | caused the interrupt. The default setting of the FPGA clears
  34. |
  35. +-------------------------------------------------------------------------*/
  36. mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  37. mtdcr (uicer, 0x00000000); /* disable all ints */
  38. mtdcr (uiccr, 0x00000020); /* set all but FPGA SMI to be non-critical */
  39. mtdcr (uicpr, 0xFFFFFF90); /* set int polarities */
  40. mtdcr (uictr, 0x10000000); /* set int trigger levels */
  41. mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
  42. mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
  43. /* Perform reset of PHY connected to PPC via register in CPLD */
  44. out8 (PHY_CTRL_ADDR, 0x2e); /* activate nRESET,FDX,F100,ANEN, enable output */
  45. for (i = 0; i < 10000000; i++) {
  46. ;
  47. }
  48. out8 (PHY_CTRL_ADDR, 0x2f); /* deactivate nRESET */
  49. return 0;
  50. }
  51. /* ************************************************************************ */
  52. int checkboard (void)
  53. /* ------------------------------------------------------------------------ --
  54. * Purpose :
  55. * Remarks :
  56. * Restrictions:
  57. * See also :
  58. * Example :
  59. * ************************************************************************ */
  60. {
  61. printf ("Exbit H/W id: %d\n", in8 (HW_ID_ADDR));
  62. return (0);
  63. }
  64. /* ************************************************************************ */
  65. phys_size_t initdram (int board_type)
  66. /* ------------------------------------------------------------------------ --
  67. * Purpose : Determines size of mounted DRAM.
  68. * Remarks : Size is determined by reading SDRAM configuration registers as
  69. * set up by sdram_init.
  70. * Restrictions:
  71. * See also :
  72. * Example :
  73. * ************************************************************************ */
  74. {
  75. ulong tot_size;
  76. ulong bank_size;
  77. ulong tmp;
  78. /*
  79. * ToDo: Move the asm init routine sdram_init() to this C file,
  80. * or even better use some common ppc4xx code available
  81. * in cpu/ppc4xx
  82. */
  83. sdram_init();
  84. tot_size = 0;
  85. mtdcr (memcfga, mem_mb0cf);
  86. tmp = mfdcr (memcfgd);
  87. if (tmp & 0x00000001) {
  88. bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  89. tot_size += bank_size;
  90. }
  91. mtdcr (memcfga, mem_mb1cf);
  92. tmp = mfdcr (memcfgd);
  93. if (tmp & 0x00000001) {
  94. bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  95. tot_size += bank_size;
  96. }
  97. mtdcr (memcfga, mem_mb2cf);
  98. tmp = mfdcr (memcfgd);
  99. if (tmp & 0x00000001) {
  100. bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  101. tot_size += bank_size;
  102. }
  103. mtdcr (memcfga, mem_mb3cf);
  104. tmp = mfdcr (memcfgd);
  105. if (tmp & 0x00000001) {
  106. bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
  107. tot_size += bank_size;
  108. }
  109. return tot_size;
  110. }