csb226.h 15 KB

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  1. /*
  2. * (C) Copyright 2000, 2001, 2002
  3. * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
  4. *
  5. * Configuration for the Cogent CSB226 board. For details see
  6. * http://www.cogcomp.com/csb_csb226.htm
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /*
  27. * include/configs/csb226.h - configuration options, board specific
  28. */
  29. #ifndef __CONFIG_H
  30. #define __CONFIG_H
  31. #define DEBUG 1
  32. /*
  33. * If we are developing, we might want to start U-Boot from ram
  34. * so we MUST NOT initialize critical regs like mem-timing ...
  35. */
  36. #define CONFIG_INIT_CRITICAL /* undef for developing */
  37. /*
  38. * High Level Configuration Options
  39. * (easy to change)
  40. */
  41. #define CONFIG_PXA250 1 /* This is an PXA250 CPU */
  42. #define CONFIG_CSB226 1 /* on a CSB226 board */
  43. #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  44. /* for timer/console/ethernet */
  45. /*
  46. * Hardware drivers
  47. */
  48. /*
  49. * select serial console configuration
  50. */
  51. #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
  52. /* allow to overwrite serial and ethaddr */
  53. #define CONFIG_ENV_OVERWRITE
  54. #define CONFIG_BAUDRATE 19200
  55. #undef CONFIG_MISC_INIT_R /* not used yet */
  56. #define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_DHCP|CFG_CMD_CACHE)
  57. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  58. #include <cmd_confdefs.h>
  59. #define CONFIG_BOOTDELAY 3
  60. #define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0"
  61. #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
  62. #define CONFIG_NETMASK 255.255.255.0
  63. #define CONFIG_IPADDR 192.168.1.56
  64. #define CONFIG_SERVERIP 192.168.1.5
  65. #define CONFIG_BOOTCOMMAND "bootm 0x40000"
  66. #define CONFIG_SHOW_BOOT_PROGRESS
  67. #define CONFIG_CMDLINE_TAG 1
  68. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  69. #define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
  70. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  71. #endif
  72. /*
  73. * Miscellaneous configurable options
  74. */
  75. /*
  76. * Size of malloc() pool; this lives below the uppermost 128 KiB which are
  77. * used for the RAM copy of the uboot code
  78. *
  79. */
  80. #define CFG_MALLOC_LEN (128*1024)
  81. #define CFG_LONGHELP /* undef to save memory */
  82. #define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
  83. #define CFG_CBSIZE 128 /* Console I/O Buffer Size */
  84. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  85. #define CFG_MAXARGS 16 /* max number of command args */
  86. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  87. #define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
  88. #define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
  89. #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
  90. #define CFG_LOAD_ADDR 0xa3000000 /* default load address */
  91. /* RS: where is this documented? */
  92. /* RS: is this where U-Boot is */
  93. /* RS: relocated to in RAM? */
  94. #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
  95. /* RS: the oscillator is actually 3680130?? */
  96. #define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
  97. /* 0101000001 */
  98. /* ^^^^^ Memory Speed 99.53 MHz */
  99. /* ^^ Run Mode Speed = 2x Mem Speed */
  100. /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
  101. #define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
  102. /* valid baudrates */
  103. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  104. /*
  105. * Network chip
  106. */
  107. #define CONFIG_DRIVER_CS8900 1
  108. #define CS8900_BUS32 1
  109. #define CS8900_BASE 0x08000000
  110. /*
  111. * Stack sizes
  112. *
  113. * The stack sizes are set up in start.S using the settings below
  114. */
  115. #define CONFIG_STACKSIZE (128*1024) /* regular stack */
  116. #ifdef CONFIG_USE_IRQ
  117. #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
  118. #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
  119. #endif
  120. /*
  121. * Physical Memory Map
  122. */
  123. #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  124. #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
  125. #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
  126. #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
  127. #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
  128. #define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */
  129. #define CFG_DRAM_SIZE 0x02000000
  130. #define CFG_FLASH_BASE PHYS_FLASH_1
  131. # if 0
  132. /* FIXME: switch to _documented_ registers */
  133. /*
  134. * GPIO settings
  135. *
  136. * GP15 == nCS1 is 1
  137. * GP24 == SFRM is 1
  138. * GP25 == TXD is 1
  139. * GP33 == nCS5 is 1
  140. * GP39 == FFTXD is 1
  141. * GP41 == RTS is 1
  142. * GP47 == TXD is 1
  143. * GP49 == nPWE is 1
  144. * GP62 == LED_B is 1
  145. * GP63 == TDM_OE is 1
  146. * GP78 == nCS2 is 1
  147. * GP79 == nCS3 is 1
  148. * GP80 == nCS4 is 1
  149. */
  150. #define CFG_GPSR0_VAL 0x03008000
  151. #define CFG_GPSR1_VAL 0xC0028282
  152. #define CFG_GPSR2_VAL 0x0001C000
  153. /* GP02 == DON_RST is 0
  154. * GP23 == SCLK is 0
  155. * GP45 == USB_ACT is 0
  156. * GP60 == PLLEN is 0
  157. * GP61 == LED_A is 0
  158. * GP73 == SWUPD_LED is 0
  159. */
  160. #define CFG_GPCR0_VAL 0x00800004
  161. #define CFG_GPCR1_VAL 0x30002000
  162. #define CFG_GPCR2_VAL 0x00000100
  163. /* GP00 == DON_READY is input
  164. * GP01 == DON_OK is input
  165. * GP02 == DON_RST is output
  166. * GP03 == RESET_IND is input
  167. * GP07 == RES11 is input
  168. * GP09 == RES12 is input
  169. * GP11 == SWUPDATE is input
  170. * GP14 == nPOWEROK is input
  171. * GP15 == nCS1 is output
  172. * GP17 == RES22 is input
  173. * GP18 == RDY is input
  174. * GP23 == SCLK is output
  175. * GP24 == SFRM is output
  176. * GP25 == TXD is output
  177. * GP26 == RXD is input
  178. * GP32 == RES21 is input
  179. * GP33 == nCS5 is output
  180. * GP34 == FFRXD is input
  181. * GP35 == CTS is input
  182. * GP39 == FFTXD is output
  183. * GP41 == RTS is output
  184. * GP42 == USB_OK is input
  185. * GP45 == USB_ACT is output
  186. * GP46 == RXD is input
  187. * GP47 == TXD is output
  188. * GP49 == nPWE is output
  189. * GP58 == nCPUBUSINT is input
  190. * GP59 == LANINT is input
  191. * GP60 == PLLEN is output
  192. * GP61 == LED_A is output
  193. * GP62 == LED_B is output
  194. * GP63 == TDM_OE is output
  195. * GP64 == nDSPINT is input
  196. * GP65 == STRAP0 is input
  197. * GP67 == STRAP1 is input
  198. * GP69 == STRAP2 is input
  199. * GP70 == STRAP3 is input
  200. * GP71 == STRAP4 is input
  201. * GP73 == SWUPD_LED is output
  202. * GP78 == nCS2 is output
  203. * GP79 == nCS3 is output
  204. * GP80 == nCS4 is output
  205. */
  206. #define CFG_GPDR0_VAL 0x03808004
  207. #define CFG_GPDR1_VAL 0xF002A282
  208. #define CFG_GPDR2_VAL 0x0001C200
  209. /* GP15 == nCS1 is AF10
  210. * GP18 == RDY is AF01
  211. * GP23 == SCLK is AF10
  212. * GP24 == SFRM is AF10
  213. * GP25 == TXD is AF10
  214. * GP26 == RXD is AF01
  215. * GP33 == nCS5 is AF10
  216. * GP34 == FFRXD is AF01
  217. * GP35 == CTS is AF01
  218. * GP39 == FFTXD is AF10
  219. * GP41 == RTS is AF10
  220. * GP46 == RXD is AF10
  221. * GP47 == TXD is AF01
  222. * GP49 == nPWE is AF10
  223. * GP78 == nCS2 is AF10
  224. * GP79 == nCS3 is AF10
  225. * GP80 == nCS4 is AF10
  226. */
  227. #define CFG_GAFR0_L_VAL 0x80000000
  228. #define CFG_GAFR0_U_VAL 0x001A8010
  229. #define CFG_GAFR1_L_VAL 0x60088058
  230. #define CFG_GAFR1_U_VAL 0x00000008
  231. #define CFG_GAFR2_L_VAL 0xA0000000
  232. #define CFG_GAFR2_U_VAL 0x00000002
  233. /* FIXME: set GPIO_RER/FER */
  234. /* RDH = 1
  235. * PH = 1
  236. * VFS = 1
  237. * BFS = 1
  238. * SSS = 1
  239. */
  240. #define CFG_PSSR_VAL 0x37
  241. /*
  242. * Memory settings
  243. *
  244. * This is the configuration for nCS0/1 -> flash banks
  245. * configuration for nCS1:
  246. * [31] 0 - Slower Device
  247. * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
  248. * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
  249. * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
  250. * [19] 1 - 16 Bit bus width
  251. * [18:16] 000 - nonburst RAM or FLASH
  252. * configuration for nCS0:
  253. * [15] 0 - Slower Device
  254. * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
  255. * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
  256. * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
  257. * [03] 1 - 16 Bit bus width
  258. * [02:00] 000 - nonburst RAM or FLASH
  259. */
  260. #define CFG_MSC0_VAL 0x25b825b8 /* flash banks */
  261. /* This is the configuration for nCS2/3 -> TDM-Switch, DSP
  262. * configuration for nCS3: DSP
  263. * [31] 0 - Slower Device
  264. * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
  265. * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
  266. * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
  267. * [19] 1 - 16 Bit bus width
  268. * [18:16] 100 - variable latency I/O
  269. * configuration for nCS2: TDM-Switch
  270. * [15] 0 - Slower Device
  271. * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
  272. * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
  273. * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
  274. * [03] 1 - 16 Bit bus width
  275. * [02:00] 100 - variable latency I/O
  276. */
  277. #define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */
  278. /* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
  279. *
  280. * configuration for nCS5: LAN Controller
  281. * [31] 0 - Slower Device
  282. * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
  283. * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
  284. * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
  285. * [19] 1 - 16 Bit bus width
  286. * [18:16] 100 - variable latency I/O
  287. * configuration for nCS4: ExtBus
  288. * [15] 0 - Slower Device
  289. * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
  290. * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
  291. * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
  292. * [03] 1 - 16 Bit bus width
  293. * [02:00] 100 - variable latency I/O
  294. */
  295. #define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */
  296. /* MDCNFG: SDRAM Configuration Register
  297. *
  298. * [31:29] 000 - reserved
  299. * [28] 0 - no SA1111 compatiblity mode
  300. * [27] 0 - latch return data with return clock
  301. * [26] 0 - alternate addressing for pair 2/3
  302. * [25:24] 00 - timings
  303. * [23] 0 - internal banks in lower partition 2/3 (not used)
  304. * [22:21] 00 - row address bits for partition 2/3 (not used)
  305. * [20:19] 00 - column address bits for partition 2/3 (not used)
  306. * [18] 0 - SDRAM partition 2/3 width is 32 bit
  307. * [17] 0 - SDRAM partition 3 disabled
  308. * [16] 0 - SDRAM partition 2 disabled
  309. * [15:13] 000 - reserved
  310. * [12] 1 - SA1111 compatiblity mode
  311. * [11] 1 - latch return data with return clock
  312. * [10] 0 - no alternate addressing for pair 0/1
  313. * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk
  314. * [7] 1 - 4 internal banks in lower partition pair
  315. * [06:05] 10 - 13 row address bits for partition 0/1
  316. * [04:03] 01 - 9 column address bits for partition 0/1
  317. * [02] 0 - SDRAM partition 0/1 width is 32 bit
  318. * [01] 0 - disable SDRAM partition 1
  319. * [00] 1 - enable SDRAM partition 0
  320. */
  321. /* use the configuration above but disable partition 0 */
  322. #define CFG_MDCNFG_VAL 0x000019c8
  323. /* MDREFR: SDRAM Refresh Control Register
  324. *
  325. * [32:26] 0 - reserved
  326. * [25] 0 - K2FREE: not free running
  327. * [24] 0 - K1FREE: not free running
  328. * [23] 1 - K0FREE: not free running
  329. * [22] 0 - SLFRSH: self refresh disabled
  330. * [21] 0 - reserved
  331. * [20] 0 - APD: no auto power down
  332. * [19] 0 - K2DB2: SDCLK2 is MemClk
  333. * [18] 0 - K2RUN: disable SDCLK2
  334. * [17] 0 - K1DB2: SDCLK1 is MemClk
  335. * [16] 1 - K1RUN: enable SDCLK1
  336. * [15] 1 - E1PIN: SDRAM clock enable
  337. * [14] 1 - K0DB2: SDCLK0 is MemClk
  338. * [13] 0 - K0RUN: disable SDCLK0
  339. * [12] 1 - E0PIN: disable SDCKE0
  340. * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
  341. */
  342. #define CFG_MDREFR_VAL 0x0081D018
  343. /* MDMRS: Mode Register Set Configuration Register
  344. *
  345. * [31] 0 - reserved
  346. * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
  347. * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
  348. * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
  349. * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
  350. * [15] 0 - reserved
  351. * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
  352. * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
  353. * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
  354. * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
  355. */
  356. #define CFG_MDMRS_VAL 0x00020022
  357. /*
  358. * PCMCIA and CF Interfaces
  359. */
  360. #define CFG_MECR_VAL 0x00000000
  361. #define CFG_MCMEM0_VAL 0x00000000
  362. #define CFG_MCMEM1_VAL 0x00000000
  363. #define CFG_MCATT0_VAL 0x00000000
  364. #define CFG_MCATT1_VAL 0x00000000
  365. #define CFG_MCIO0_VAL 0x00000000
  366. #define CFG_MCIO1_VAL 0x00000000
  367. #endif
  368. /*
  369. * GPIO settings
  370. */
  371. #define CFG_GPSR0_VAL 0xFFFFFFFF
  372. #define CFG_GPSR1_VAL 0xFFFFFFFF
  373. #define CFG_GPSR2_VAL 0xFFFFFFFF
  374. #define CFG_GPCR0_VAL 0x08022080
  375. #define CFG_GPCR1_VAL 0x00000000
  376. #define CFG_GPCR2_VAL 0x00000000
  377. #define CFG_GPDR0_VAL 0xCD82A878
  378. #define CFG_GPDR1_VAL 0xFCFFAB80
  379. #define CFG_GPDR2_VAL 0x0001FFFF
  380. #define CFG_GAFR0_L_VAL 0x80000000
  381. #define CFG_GAFR0_U_VAL 0xA5254010
  382. #define CFG_GAFR1_L_VAL 0x599A9550
  383. #define CFG_GAFR1_U_VAL 0xAAA5AAAA
  384. #define CFG_GAFR2_L_VAL 0xAAAAAAAA
  385. #define CFG_GAFR2_U_VAL 0x00000002
  386. /* FIXME: set GPIO_RER/FER */
  387. #define CFG_PSSR_VAL 0x20
  388. /*
  389. * Memory settings
  390. */
  391. #define CFG_MSC0_VAL 0x2ef15af0
  392. #define CFG_MSC1_VAL 0x00003ff4
  393. #define CFG_MSC2_VAL 0x7ff07ff0
  394. #define CFG_MDCNFG_VAL 0x09a909a9
  395. #define CFG_MDREFR_VAL 0x038ff030
  396. #define CFG_MDMRS_VAL 0x00220022
  397. /*
  398. * PCMCIA and CF Interfaces
  399. */
  400. #define CFG_MECR_VAL 0x00000000
  401. #define CFG_MCMEM0_VAL 0x00000000
  402. #define CFG_MCMEM1_VAL 0x00000000
  403. #define CFG_MCATT0_VAL 0x00000000
  404. #define CFG_MCATT1_VAL 0x00000000
  405. #define CFG_MCIO0_VAL 0x00000000
  406. #define CFG_MCIO1_VAL 0x00000000
  407. #define CSB226_USER_LED0 0x00000008
  408. #define CSB226_USER_LED1 0x00000010
  409. #define CSB226_USER_LED2 0x00000020
  410. /*
  411. * FLASH and environment organization
  412. */
  413. #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  414. #define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
  415. /* timeout values are in ticks */
  416. #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
  417. #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
  418. #define CFG_ENV_IS_IN_FLASH 1
  419. #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000)
  420. /* Addr of Environment Sector */
  421. #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  422. #endif /* __CONFIG_H */