clock.c 9.2 KB

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  1. /*
  2. * clock.c
  3. *
  4. * clocks for AM33XX based boards
  5. *
  6. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. #include <common.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/clock.h>
  21. #include <asm/arch/hardware.h>
  22. #include <asm/io.h>
  23. #define PRCM_MOD_EN 0x2
  24. #define PRCM_FORCE_WAKEUP 0x2
  25. #define PRCM_FUNCTL 0x0
  26. #define PRCM_EMIF_CLK_ACTIVITY BIT(2)
  27. #define PRCM_L3_GCLK_ACTIVITY BIT(4)
  28. #define PLL_BYPASS_MODE 0x4
  29. #define ST_MN_BYPASS 0x00000100
  30. #define ST_DPLL_CLK 0x00000001
  31. #define CLK_SEL_MASK 0x7ffff
  32. #define CLK_DIV_MASK 0x1f
  33. #define CLK_DIV2_MASK 0x7f
  34. #define CLK_SEL_SHIFT 0x8
  35. #define CLK_MODE_SEL 0x7
  36. #define CLK_MODE_MASK 0xfffffff8
  37. #define CLK_DIV_SEL 0xFFFFFFE0
  38. #define CPGMAC0_IDLE 0x30000
  39. #define DPLL_CLKDCOLDO_GATE_CTRL 0x300
  40. const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
  41. const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
  42. const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
  43. const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
  44. static void enable_interface_clocks(void)
  45. {
  46. /* Enable all the Interconnect Modules */
  47. writel(PRCM_MOD_EN, &cmper->l3clkctrl);
  48. while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
  49. ;
  50. writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
  51. while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
  52. ;
  53. writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
  54. while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
  55. ;
  56. writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
  57. while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
  58. ;
  59. writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
  60. while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
  61. ;
  62. writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
  63. while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
  64. ;
  65. writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
  66. while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
  67. ;
  68. }
  69. /*
  70. * Force power domain wake up transition
  71. * Ensure that the corresponding interface clock is active before
  72. * using the peripheral
  73. */
  74. static void power_domain_wkup_transition(void)
  75. {
  76. writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
  77. writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
  78. writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
  79. writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
  80. writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
  81. }
  82. /*
  83. * Enable the peripheral clock for required peripherals
  84. */
  85. static void enable_per_clocks(void)
  86. {
  87. /* Enable the control module though RBL would have done it*/
  88. writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
  89. while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
  90. ;
  91. /* Enable the module clock */
  92. writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
  93. while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
  94. ;
  95. /* Select the Master osc 24 MHZ as Timer2 clock source */
  96. writel(0x1, &cmdpll->clktimer2clk);
  97. /* UART0 */
  98. writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
  99. while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
  100. ;
  101. /* UART1 */
  102. #ifdef CONFIG_SERIAL2
  103. writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
  104. while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
  105. ;
  106. #endif /* CONFIG_SERIAL2 */
  107. /* UART2 */
  108. #ifdef CONFIG_SERIAL3
  109. writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
  110. while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
  111. ;
  112. #endif /* CONFIG_SERIAL3 */
  113. /* UART3 */
  114. #ifdef CONFIG_SERIAL4
  115. writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
  116. while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
  117. ;
  118. #endif /* CONFIG_SERIAL4 */
  119. /* UART4 */
  120. #ifdef CONFIG_SERIAL5
  121. writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
  122. while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
  123. ;
  124. #endif /* CONFIG_SERIAL5 */
  125. /* UART5 */
  126. #ifdef CONFIG_SERIAL6
  127. writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
  128. while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
  129. ;
  130. #endif /* CONFIG_SERIAL6 */
  131. /* MMC0*/
  132. writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
  133. while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
  134. ;
  135. /* i2c0 */
  136. writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
  137. while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
  138. ;
  139. /* gpio1 module */
  140. writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
  141. while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
  142. ;
  143. /* gpio2 module */
  144. writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
  145. while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
  146. ;
  147. /* gpio3 module */
  148. writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
  149. while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
  150. ;
  151. /* i2c1 */
  152. writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
  153. while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
  154. ;
  155. /* Ethernet */
  156. writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
  157. while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
  158. ;
  159. /* spi0 */
  160. writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
  161. while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
  162. ;
  163. /* RTC */
  164. writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
  165. while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
  166. ;
  167. /* MUSB */
  168. writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
  169. while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
  170. ;
  171. }
  172. static void mpu_pll_config(void)
  173. {
  174. u32 clkmode, clksel, div_m2;
  175. clkmode = readl(&cmwkup->clkmoddpllmpu);
  176. clksel = readl(&cmwkup->clkseldpllmpu);
  177. div_m2 = readl(&cmwkup->divm2dpllmpu);
  178. /* Set the PLL to bypass Mode */
  179. writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
  180. while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
  181. ;
  182. clksel = clksel & (~CLK_SEL_MASK);
  183. clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
  184. writel(clksel, &cmwkup->clkseldpllmpu);
  185. div_m2 = div_m2 & ~CLK_DIV_MASK;
  186. div_m2 = div_m2 | MPUPLL_M2;
  187. writel(div_m2, &cmwkup->divm2dpllmpu);
  188. clkmode = clkmode | CLK_MODE_SEL;
  189. writel(clkmode, &cmwkup->clkmoddpllmpu);
  190. while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
  191. ;
  192. }
  193. static void core_pll_config(void)
  194. {
  195. u32 clkmode, clksel, div_m4, div_m5, div_m6;
  196. clkmode = readl(&cmwkup->clkmoddpllcore);
  197. clksel = readl(&cmwkup->clkseldpllcore);
  198. div_m4 = readl(&cmwkup->divm4dpllcore);
  199. div_m5 = readl(&cmwkup->divm5dpllcore);
  200. div_m6 = readl(&cmwkup->divm6dpllcore);
  201. /* Set the PLL to bypass Mode */
  202. writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
  203. while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
  204. ;
  205. clksel = clksel & (~CLK_SEL_MASK);
  206. clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
  207. writel(clksel, &cmwkup->clkseldpllcore);
  208. div_m4 = div_m4 & ~CLK_DIV_MASK;
  209. div_m4 = div_m4 | COREPLL_M4;
  210. writel(div_m4, &cmwkup->divm4dpllcore);
  211. div_m5 = div_m5 & ~CLK_DIV_MASK;
  212. div_m5 = div_m5 | COREPLL_M5;
  213. writel(div_m5, &cmwkup->divm5dpllcore);
  214. div_m6 = div_m6 & ~CLK_DIV_MASK;
  215. div_m6 = div_m6 | COREPLL_M6;
  216. writel(div_m6, &cmwkup->divm6dpllcore);
  217. clkmode = clkmode | CLK_MODE_SEL;
  218. writel(clkmode, &cmwkup->clkmoddpllcore);
  219. while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
  220. ;
  221. }
  222. static void per_pll_config(void)
  223. {
  224. u32 clkmode, clksel, div_m2;
  225. clkmode = readl(&cmwkup->clkmoddpllper);
  226. clksel = readl(&cmwkup->clkseldpllper);
  227. div_m2 = readl(&cmwkup->divm2dpllper);
  228. /* Set the PLL to bypass Mode */
  229. writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
  230. while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
  231. ;
  232. clksel = clksel & (~CLK_SEL_MASK);
  233. clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
  234. writel(clksel, &cmwkup->clkseldpllper);
  235. div_m2 = div_m2 & ~CLK_DIV2_MASK;
  236. div_m2 = div_m2 | PERPLL_M2;
  237. writel(div_m2, &cmwkup->divm2dpllper);
  238. clkmode = clkmode | CLK_MODE_SEL;
  239. writel(clkmode, &cmwkup->clkmoddpllper);
  240. while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
  241. ;
  242. writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
  243. }
  244. void ddr_pll_config(unsigned int ddrpll_m)
  245. {
  246. u32 clkmode, clksel, div_m2;
  247. clkmode = readl(&cmwkup->clkmoddpllddr);
  248. clksel = readl(&cmwkup->clkseldpllddr);
  249. div_m2 = readl(&cmwkup->divm2dpllddr);
  250. /* Set the PLL to bypass Mode */
  251. clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
  252. writel(clkmode, &cmwkup->clkmoddpllddr);
  253. /* Wait till bypass mode is enabled */
  254. while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
  255. != ST_MN_BYPASS)
  256. ;
  257. clksel = clksel & (~CLK_SEL_MASK);
  258. clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
  259. writel(clksel, &cmwkup->clkseldpllddr);
  260. div_m2 = div_m2 & CLK_DIV_SEL;
  261. div_m2 = div_m2 | DDRPLL_M2;
  262. writel(div_m2, &cmwkup->divm2dpllddr);
  263. clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
  264. writel(clkmode, &cmwkup->clkmoddpllddr);
  265. /* Wait till dpll is locked */
  266. while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
  267. ;
  268. }
  269. void enable_emif_clocks(void)
  270. {
  271. /* Enable the EMIF_FW Functional clock */
  272. writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
  273. /* Enable EMIF0 Clock */
  274. writel(PRCM_MOD_EN, &cmper->emifclkctrl);
  275. /* Poll if module is functional */
  276. while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
  277. ;
  278. }
  279. /*
  280. * Configure the PLL/PRCM for necessary peripherals
  281. */
  282. void pll_init()
  283. {
  284. mpu_pll_config();
  285. core_pll_config();
  286. per_pll_config();
  287. /* Enable the required interconnect clocks */
  288. enable_interface_clocks();
  289. /* Power domain wake up transition */
  290. power_domain_wkup_transition();
  291. /* Enable the required peripherals */
  292. enable_per_clocks();
  293. }