Página inicial Explorar Ajuda
Registrar Entrar
phyus
/
uboot-vybrid_public
8
0
Fork 0
Arquivos Issues 0 Pull Requests 0 Wiki
Tree: 9652de7c48
Branches Tags
uboot-vybrid_pu...
/
arch
/
arm
/
include
/
asm
/
arch-u8500
/
prcmu.h

prcmu.h 2.4 KB
Histórico Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869 
  1. /*
    2. 

  2.  * Copyright (C) 2009 ST-Ericsson SA
    3. 

  3.  *
    4. 

  4.  * Copied from the Linux version:
    5. 

  5.  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
    6. 

  6.  *
    7. 

  7.  * This program is free software; you can redistribute it and/or modify
    8. 

  8.  * it under the terms of the GNU General Public License as published by
    9. 

  9.  * the Free Software Foundation; either version 2 of the License, or
    10. 

  10.  * (at your option) any later version.
    11. 

  11.  *
    12. 

  12.  * This program is distributed in the hope that it will be useful,
    13. 

  13.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    14. 

  14.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    15. 

  15.  * GNU General Public License for more details.
    16. 

  16.  *
    17. 

  17.  * You should have received a copy of the GNU General Public License
    18. 

  18.  * along with this program; if not, write to the Free Software
    19. 

  19.  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
    20. 

  20.  */
    21. 

  21. #ifndef __MACH_PRCMU_FW_V1_H
    22. 

  22. #define __MACH_PRCMU_FW_V1_H
    23. 

  23. 

  24. #define AP_EXECUTE	2
    25. 

  25. #define I2CREAD		1
    26. 

  26. #define I2C_WR_OK	1
    27. 

  27. #define I2C_RD_OK	2
    28. 

  28. #define I2CWRITE	0
    29. 

  29. 

  30. #define PRCMU_BASE			U8500_PRCMU_BASE
    31. 

  31. #define PRCM_UARTCLK_MGT_REG		(PRCMU_BASE + 0x018)
    32. 

  32. #define PRCM_MSPCLK_MGT_REG		(PRCMU_BASE + 0x01C)
    33. 

  33. #define PRCM_I2CCLK_MGT_REG		(PRCMU_BASE + 0x020)
    34. 

  34. #define PRCM_SDMMCCLK_MGT_REG		(PRCMU_BASE + 0x024)
    35. 

  35. #define PRCM_PER1CLK_MGT_REG		(PRCMU_BASE + 0x02C)
    36. 

  36. #define PRCM_PER2CLK_MGT_REG		(PRCMU_BASE + 0x030)
    37. 

  37. #define PRCM_PER3CLK_MGT_REG		(PRCMU_BASE + 0x034)
    38. 

  38. #define PRCM_PER5CLK_MGT_REG		(PRCMU_BASE + 0x038)
    39. 

  39. #define PRCM_PER6CLK_MGT_REG		(PRCMU_BASE + 0x03C)
    40. 

  40. #define PRCM_PER7CLK_MGT_REG		(PRCMU_BASE + 0x040)
    41. 

  41. 

  42. #define PRCM_ARM_IT1_CLEAR		(PRCMU_BASE + 0x48C)
    43. 

  43. #define PRCM_TCR			(PRCMU_BASE + 0x1C8)
    44. 

  44. #define PRCM_REQ_MB5			(PRCMU_BASE + 0xE44)
    45. 

  45. #define PRCM_ACK_MB5			(PRCMU_BASE + 0xDF4)
    46. 

  46. #define PRCM_XP70_CUR_PWR_STATE		(PRCMU_BASE + 0xFFC)
    47. 

  47. /* Mailbox 5 Requests */
    48. 

  48. #define PRCM_REQ_MB5_I2COPTYPE_REG	(PRCM_REQ_MB5 + 0x0)
    49. 

  49. #define PRCM_REQ_MB5_BIT_FIELDS		(PRCM_REQ_MB5 + 0x1)
    50. 

  50. #define PRCM_REQ_MB5_I2CSLAVE		(PRCM_REQ_MB5 + 0x2)
    51. 

  51. #define PRCM_REQ_MB5_I2CVAL		(PRCM_REQ_MB5 + 0x3)
    52. 

  52. 

  53. /* Mailbox 5 ACKs */
    54. 

  54. #define PRCM_ACK_MB5_STATUS	(PRCM_ACK_MB5 + 0x1)
    55. 

  55. #define PRCM_ACK_MB5_SLAVE	(PRCM_ACK_MB5 + 0x2)
    56. 

  56. #define PRCM_ACK_MB5_VAL	(PRCM_ACK_MB5 + 0x3)
    57. 

  57. 

  58. #define LOW_POWER_WAKEUP	1
    59. 

  59. #define EXE_WAKEUP		0
    60. 

  60. 

  61. #define REQ_MB5			5
    62. 

  62. 

  63. extern int prcmu_i2c_read(u8 reg, u16 slave);
    64. 

  64. extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
    65. 

  65. 

  66. void u8500_prcmu_enable(u32 *reg);
    67. 

  67. void db8500_prcmu_init(void);
    68. 

  68. 

  69. #endif /* __MACH_PRCMU_FW_V1_H */
    70.