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uboot-vybrid_pu...
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board
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ti
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sdp3430
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sdp.h

sdp.h 22 KB
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  1. /*
    2. 

  2.  * (C) Copyright 2004-2009
    3. 

  3.  * Texas Instruments Incorporated
    4. 

  4.  * Richard Woodruff <r-woodruff2@ti.com>
    5. 

  5.  *
    6. 

  6.  * See file CREDITS for list of people who contributed to this
    7. 

  7.  * project.
    8. 

  8.  *
    9. 

  9.  * This program is free software; you can redistribute it and/or
    10. 

  10.  * modify it under the terms of the GNU General Public License as
    11. 

  11.  * published by the Free Software Foundation; either version 2 of
    12. 

  12.  * the License, or (at your option) any later version.
    13. 

  13.  *
    14. 

  14.  * This program is distributed in the hope that it will be useful,
    15. 

  15.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    16. 

  16.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    17. 

  17.  * GNU General Public License for more details.
    18. 

  18.  *
    19. 

  19.  * You should have received a copy of the GNU General Public License
    20. 

  20.  * along with this program; if not, write to the Free Software
    21. 

  21.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    22. 

  22.  * MA 02111-1307 USA
    23. 

  23.  */
    24. 

  24. #ifndef _BOARD_SDP_H_
    25. 

  25. #define _BOARD_SDP_H_
    26. 

  26. 

  27. #define OFF_IN_PD	0
    28. 

  28. #define OFF_OUT_PD	0
    29. 

  29. 

  30. /*
    31. 

  31.  * IEN	- Input Enable
    32. 

  32.  * IDIS	- Input Disable
    33. 

  33.  * PTD	- Pull type Down
    34. 

  34.  * PTU	- Pull type Up
    35. 

  35.  * DIS	- Pull type selection is inactive
    36. 

  36.  * EN	- Pull type selection is active
    37. 

  37.  * M0	- Mode 0
    38. 

  38.  * The commented string gives the final mux configuration for that pin
    39. 

  39.  */
    40. 

  40. #define MUX_SDP3430()\
    41. 

  41. 	/*SDRC*/\
    42. 

  42. 	MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\
    43. 

  43. 	MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\
    44. 

  44. 	MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\
    45. 

  45. 	MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\
    46. 

  46. 	MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\
    47. 

  47. 	MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\
    48. 

  48. 	MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\
    49. 

  49. 	MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\
    50. 

  50. 	MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\
    51. 

  51. 	MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\
    52. 

  52. 	MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\
    53. 

  53. 	MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\
    54. 

  54. 	MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\
    55. 

  55. 	MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\
    56. 

  56. 	MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\
    57. 

  57. 	MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\
    58. 

  58. 	MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\
    59. 

  59. 	MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\
    60. 

  60. 	MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\
    61. 

  61. 	MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\
    62. 

  62. 	MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\
    63. 

  63. 	MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\
    64. 

  64. 	MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\
    65. 

  65. 	MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\
    66. 

  66. 	MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\
    67. 

  67. 	MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\
    68. 

  68. 	MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\
    69. 

  69. 	MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\
    70. 

  70. 	MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\
    71. 

  71. 	MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\
    72. 

  72. 	MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\
    73. 

  73. 	MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\
    74. 

  74. 	MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\
    75. 

  75. 	MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\
    76. 

  76. 	MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\
    77. 

  77. 	MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\
    78. 

  78. 	MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\
    79. 

  79. 	/*GPMC*/\
    80. 

  80. 	MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    81. 

  81. 	MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    82. 

  82. 	MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    83. 

  83. 	MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    84. 

  84. 	MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    85. 

  85. 	MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    86. 

  86. 	MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    87. 

  87. 	MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    88. 

  88. 	MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    89. 

  89. 	MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    90. 

  90. 	MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    91. 

  91. 	MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    92. 

  92. 	MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    93. 

  93. 	MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    94. 

  94. 	MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    95. 

  95. 	MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    96. 

  96. 	MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    97. 

  97. 	MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    98. 

  98. 	MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    99. 

  99. 	MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    100. 

  100. 	MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    101. 

  101. 	MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    102. 

  102. 	MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    103. 

  103. 	MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    104. 

  104. 	MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    105. 

  105. 	MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    106. 

  106. 	MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
    107. 

  107. 	MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
    108. 

  108. 	MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
    109. 

  109. 	MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
    110. 

  110. 	MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\
    111. 

  111. 	MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\
    112. 

  112. 	MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\
    113. 

  113. 	MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\
    114. 

  114. 	MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    115. 

  115. 	MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    116. 

  116. 	MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    117. 

  117. 	MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    118. 

  118. 	MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    119. 

  119. 	MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\
    120. 

  120. 	MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    121. 

  121. 	MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
    122. 

  122. 	MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
    123. 

  123. 	MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\
    124. 

  124. 	MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\
    125. 

  125. 	/*DSS*/\
    126. 

  126. 	MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    127. 

  127. 	MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    128. 

  128. 	MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    129. 

  129. 	MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    130. 

  130. 	MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    131. 

  131. 	MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    132. 

  132. 	MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    133. 

  133. 	MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    134. 

  134. 	MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    135. 

  135. 	MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    136. 

  136. 	MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    137. 

  137. 	MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    138. 

  138. 	MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    139. 

  139. 	MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    140. 

  140. 	MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    141. 

  141. 	MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    142. 

  142. 	MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    143. 

  143. 	MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    144. 

  144. 	MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    145. 

  145. 	MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    146. 

  146. 	MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    147. 

  147. 	MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    148. 

  148. 	MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    149. 

  149. 	MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    150. 

  150. 	MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    151. 

  151. 	MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    152. 

  152. 	MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    153. 

  153. 	MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    154. 

  154. 	/*CAMERA*/\
    155. 

  155. 	MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\
    156. 

  156. 	MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\
    157. 

  157. 	MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    158. 

  158. 	MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\
    159. 

  159. 	MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\
    160. 

  160. 	MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\
    161. 

  161. 	MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\
    162. 

  162. 	MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    163. 

  163. 	MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    164. 

  164. 	MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    165. 

  165. 	MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    166. 

  166. 	MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    167. 

  167. 	MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    168. 

  168. 	MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    169. 

  169. 	MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    170. 

  170. 	MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    171. 

  171. 	MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    172. 

  172. 	MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    173. 

  173. 	MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\
    174. 

  174. 	MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    175. 

  175. 	MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    176. 

  176. 	MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    177. 

  177. 	MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    178. 

  178. 	MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    179. 

  179. 	/*Audio InterfACe */\
    180. 

  180. 	MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    181. 

  181. 	MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    182. 

  182. 	MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    183. 

  183. 	MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    184. 

  184. 	/*Expansion Card */\
    185. 

  185. 	MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
    186. 

  186. 	MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
    187. 

  187. 	MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
    188. 

  188. 	MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
    189. 

  189. 	MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
    190. 

  190. 	MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
    191. 

  191. 	MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\
    192. 

  192. 	MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\
    193. 

  193. 	MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\
    194. 

  194. 	MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\
    195. 

  195. 	/*Wireless LAN */\
    196. 

  196. 	MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    197. 

  197. 	MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\
    198. 

  198. 	MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\
    199. 

  199. 	MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\
    200. 

  200. 	MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\
    201. 

  201. 	MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\
    202. 

  202. 	MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\
    203. 

  203. 	MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\
    204. 

  204. 	MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\
    205. 

  205. 	MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\
    206. 

  206. 	/*Bluetooth*/\
    207. 

  207. 	MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    208. 

  208. 	MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    209. 

  209. 	MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    210. 

  210. 	MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    211. 

  211. 	MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\
    212. 

  212. 	MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    213. 

  213. 	MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    214. 

  214. 	MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    215. 

  215. 	/*Modem Interface */\
    216. 

  216. 	MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    217. 

  217. 	MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    218. 

  218. 	MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
    219. 

  219. 	MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    220. 

  220. 	MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\
    221. 

  221. 	MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\
    222. 

  222. 	MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\
    223. 

  223. 	MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\
    224. 

  224. 	MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    225. 

  225. 	MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\
    226. 

  226. 	MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    227. 

  227. 	MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    228. 

  228. 	MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\
    229. 

  229. 	MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    230. 

  230. 	MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    231. 

  231. 	/*Serial Interface*/\
    232. 

  232. 	MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\
    233. 

  233. 	MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    234. 

  234. 	MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    235. 

  235. 	MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    236. 

  236. 	MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    237. 

  237. 	MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
    238. 

  238. 	MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    239. 

  239. 	MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    240. 

  240. 	MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    241. 

  241. 	MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    242. 

  242. 	MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    243. 

  243. 	MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    244. 

  244. 	MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    245. 

  245. 	MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    246. 

  246. 	MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    247. 

  247. 	MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    248. 

  248. 	/* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\
    249. 

  249. 	MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\
    250. 

  250. 	MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\
    251. 

  251. 	MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\
    252. 

  252. 	MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\
    253. 

  253. 	MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\
    254. 

  254. 	MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\
    255. 

  255. 	MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\
    256. 

  256. 	MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\
    257. 

  257. 	MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\
    258. 

  258. 	MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    259. 

  259. 	MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    260. 

  260. 	MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    261. 

  261. 	MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
    262. 

  262. 	MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\
    263. 

  263. 	MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\
    264. 

  264. 	MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\
    265. 

  265. 	MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    266. 

  266. 	MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    267. 

  267. 	MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    268. 

  268. 	MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\
    269. 

  269. 	MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\
    270. 

  270. 	/*Control and debug */\
    271. 

  271. 	MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\
    272. 

  272. 	MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\
    273. 

  273. 	MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\
    274. 

  274. 	MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\
    275. 

  275. 	MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\
    276. 

  276. 	MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\
    277. 

  277. 	MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\
    278. 

  278. 	MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\
    279. 

  279. 	MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\
    280. 

  280. 	MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\
    281. 

  281. 	MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\
    282. 

  282. 	MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\
    283. 

  283. 	MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\
    284. 

  284. 	MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\
    285. 

  285. 	MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\
    286. 

  286. 	MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\
    287. 

  287. 	MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\
    288. 

  288. 	MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    289. 

  289. 	MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    290. 

  290. 	MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\
    291. 

  291. 	MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\
    292. 

  292. 	MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\
    293. 

  293. 	MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\
    294. 

  294. 	MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\
    295. 

  295. 	MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\
    296. 

  296. 	MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    297. 

  297. 	MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    298. 

  298. 	MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    299. 

  299. 	MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    300. 

  300. 	MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    301. 

  301. 	MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    302. 

  302. 	MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    303. 

  303. 	MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    304. 

  304. 	MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    305. 

  305. 	MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    306. 

  306. 	MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    307. 

  307. 	MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    308. 

  308. 	/*Die to Die */\
    309. 

  309. 	MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\
    310. 

  310. 	MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\
    311. 

  311. 	MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\
    312. 

  312. 	MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\
    313. 

  313. 	MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\
    314. 

  314. 	MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\
    315. 

  315. 	MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\
    316. 

  316. 	MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\
    317. 

  317. 	MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\
    318. 

  318. 	MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\
    319. 

  319. 	MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\
    320. 

  320. 	MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\
    321. 

  321. 	MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\
    322. 

  322. 	MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\
    323. 

  323. 	MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\
    324. 

  324. 	MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\
    325. 

  325. 	MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\
    326. 

  326. 	MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\
    327. 

  327. 	MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\
    328. 

  328. 	MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\
    329. 

  329. 	MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\
    330. 

  330. 	MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\
    331. 

  331. 	MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\
    332. 

  332. 	MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\
    333. 

  333. 	MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\
    334. 

  334. 	MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\
    335. 

  335. 	MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\
    336. 

  336. 	MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\
    337. 

  337. 	MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\
    338. 

  338. 	MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\
    339. 

  339. 	MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\
    340. 

  340. 	MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\
    341. 

  341. 	MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\
    342. 

  342. 	MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\
    343. 

  343. 	MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\
    344. 

  344. 	MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\
    345. 

  345. 	MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\
    346. 

  346. 	MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    347. 

  347. 	MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\
    348. 

  348. 	MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\
    349. 

  349. 	MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    350. 

  350. 	MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    351. 

  351. 	MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
    352. 

  352. 	MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\
    353. 

  353. 	MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    354. 

  354. 	MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    355. 

  355. 	MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    356. 

  356. 	MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    357. 

  357. 	MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    358. 

  358. 	MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    359. 

  359. 	MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    360. 

  360. 	MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    361. 

  361. 	MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    362. 

  362. 	MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    363. 

  363. 	MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\
    364. 

  364. 	MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\
    365. 

  365. 	MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    366. 

  366. 	MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\
    367. 

  367. 	MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    368. 

  368. 	MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    369. 

  369. 	MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    370. 

  370. 	MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    371. 

  371. 	MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\
    372. 

  372. 	MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\
    373. 

  373. 	MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\
    374. 

  374. 	MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/
    375. 

  375. 

  376. /*
    377. 

  377.  * GPMC Timing definitions for SDP3430
    378. 

  378.  * at L3 = 166Mhz
    379. 

  379.  */
    380. 

  380. 

  381. /* Timing definitions for GPMC controller for Sibley NOR */
    382. 

  382. #define SDP3430_NOR_GPMC_CONF1 0x00001200
    383. 

  383. #define SDP3430_NOR_GPMC_CONF2 0x001F1F00
    384. 

  384. #define SDP3430_NOR_GPMC_CONF3 0x00080802
    385. 

  385. #define SDP3430_NOR_GPMC_CONF4 0x1C091C09
    386. 

  386. #define SDP3430_NOR_GPMC_CONF5 0x01131F1F
    387. 

  387. #define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2
    388. 

  388. 

  389. /*
    390. 

  390.  * Timing definitions for GPMC controller for Debug Board
    391. 

  391.  * Debug board contains access to ethernet and DIP Switch setting
    392. 

  392.  * information etc.
    393. 

  393.  */
    394. 

  394. #define SDP3430_DEBUG_GPMC_CONF1 0x00611200
    395. 

  395. #define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01
    396. 

  396. #define SDP3430_DEBUG_GPMC_CONF3 0x00080803
    397. 

  397. #define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09
    398. 

  398. #define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F
    399. 

  399. #define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4
    400. 

  400. 

  401. /* Timing defintions for GPMC OneNAND */
    402. 

  402. #define SDP3430_ONENAND_GPMC_CONF1 0x00001200
    403. 

  403. #define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01
    404. 

  404. #define SDP3430_ONENAND_GPMC_CONF3 0x00030301
    405. 

  405. #define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04
    406. 

  406. #define SDP3430_ONENAND_GPMC_CONF5 0x010F1010
    407. 

  407. #define SDP3430_ONENAND_GPMC_CONF6 0x1F060000
    408. 

  408. 

  409. /* GPMC definitions for GPMC NAND */
    410. 

  410. #define SDP3430_NAND_GPMC_CONF1 0x00000800
    411. 

  411. #define SDP3430_NAND_GPMC_CONF2 0x00141400
    412. 

  412. #define SDP3430_NAND_GPMC_CONF3 0x00141400
    413. 

  413. #define SDP3430_NAND_GPMC_CONF4 0x0F010F01
    414. 

  414. #define SDP3430_NAND_GPMC_CONF5 0x010C1414
    415. 

  415. #define SDP3430_NAND_GPMC_CONF6 0x1F040A80
    416. 

  416. 

  417. #endif /* _BOARD_SDP_H_ */
    418.