am335x_spl_bch.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238
  1. /*
  2. * (C) Copyright 2012
  3. * Konstantin Kozhevnikov, Cogent Embedded
  4. *
  5. * based on nand_spl_simple code
  6. *
  7. * (C) Copyright 2006-2008
  8. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc.
  23. */
  24. #include <common.h>
  25. #include <nand.h>
  26. #include <asm/io.h>
  27. #include <linux/mtd/nand_ecc.h>
  28. static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  29. static nand_info_t mtd;
  30. static struct nand_chip nand_chip;
  31. #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
  32. CONFIG_SYS_NAND_ECCSIZE)
  33. #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
  34. /*
  35. * NAND command for large page NAND devices (2k)
  36. */
  37. static int nand_command(int block, int page, uint32_t offs,
  38. u8 cmd)
  39. {
  40. struct nand_chip *this = mtd.priv;
  41. int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  42. void (*hwctrl)(struct mtd_info *mtd, int cmd,
  43. unsigned int ctrl) = this->cmd_ctrl;
  44. while (!this->dev_ready(&mtd))
  45. ;
  46. /* Emulate NAND_CMD_READOOB */
  47. if (cmd == NAND_CMD_READOOB) {
  48. offs += CONFIG_SYS_NAND_PAGE_SIZE;
  49. cmd = NAND_CMD_READ0;
  50. }
  51. /* Begin command latch cycle */
  52. hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  53. if (cmd == NAND_CMD_RESET) {
  54. hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  55. while (!this->dev_ready(&mtd))
  56. ;
  57. return 0;
  58. }
  59. /* Shift the offset from byte addressing to word addressing. */
  60. if (this->options & NAND_BUSWIDTH_16)
  61. offs >>= 1;
  62. /* Set ALE and clear CLE to start address cycle */
  63. /* Column address */
  64. hwctrl(&mtd, offs & 0xff,
  65. NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
  66. hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
  67. /* Row address */
  68. hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
  69. hwctrl(&mtd, ((page_addr >> 8) & 0xff),
  70. NAND_CTRL_ALE); /* A[27:20] */
  71. #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
  72. /* One more address cycle for devices > 128MiB */
  73. hwctrl(&mtd, (page_addr >> 16) & 0x0f,
  74. NAND_CTRL_ALE); /* A[31:28] */
  75. #endif
  76. hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  77. if (cmd == NAND_CMD_READ0) {
  78. /* Latch in address */
  79. hwctrl(&mtd, NAND_CMD_READSTART,
  80. NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  81. hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  82. /*
  83. * Wait a while for the data to be ready
  84. */
  85. while (!this->dev_ready(&mtd))
  86. ;
  87. } else if (cmd == NAND_CMD_RNDOUT) {
  88. hwctrl(&mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
  89. NAND_CTRL_CHANGE);
  90. hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  91. }
  92. return 0;
  93. }
  94. static int nand_is_bad_block(int block)
  95. {
  96. struct nand_chip *this = mtd.priv;
  97. nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
  98. NAND_CMD_READOOB);
  99. /*
  100. * Read one byte (or two if it's a 16 bit chip).
  101. */
  102. if (this->options & NAND_BUSWIDTH_16) {
  103. if (readw(this->IO_ADDR_R) != 0xffff)
  104. return 1;
  105. } else {
  106. if (readb(this->IO_ADDR_R) != 0xff)
  107. return 1;
  108. }
  109. return 0;
  110. }
  111. static int nand_read_page(int block, int page, void *dst)
  112. {
  113. struct nand_chip *this = mtd.priv;
  114. u_char ecc_calc[ECCTOTAL];
  115. u_char ecc_code[ECCTOTAL];
  116. u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
  117. int i;
  118. int eccsize = CONFIG_SYS_NAND_ECCSIZE;
  119. int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
  120. int eccsteps = ECCSTEPS;
  121. uint8_t *p = dst;
  122. uint32_t data_pos = 0;
  123. uint8_t *oob = &oob_data[0] + nand_ecc_pos[0];
  124. uint32_t oob_pos = eccsize * eccsteps + nand_ecc_pos[0];
  125. nand_command(block, page, 0, NAND_CMD_READ0);
  126. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  127. this->ecc.hwctl(&mtd, NAND_ECC_READ);
  128. nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
  129. this->read_buf(&mtd, p, eccsize);
  130. nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
  131. this->read_buf(&mtd, oob, eccbytes);
  132. this->ecc.calculate(&mtd, p, &ecc_calc[i]);
  133. data_pos += eccsize;
  134. oob_pos += eccbytes;
  135. oob += eccbytes;
  136. }
  137. /* Pick the ECC bytes out of the oob data */
  138. for (i = 0; i < ECCTOTAL; i++)
  139. ecc_code[i] = oob_data[nand_ecc_pos[i]];
  140. eccsteps = ECCSTEPS;
  141. p = dst;
  142. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  143. /* No chance to do something with the possible error message
  144. * from correct_data(). We just hope that all possible errors
  145. * are corrected by this routine.
  146. */
  147. this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
  148. }
  149. return 0;
  150. }
  151. int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
  152. {
  153. unsigned int block, lastblock;
  154. unsigned int page;
  155. /*
  156. * offs has to be aligned to a page address!
  157. */
  158. block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
  159. lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
  160. page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
  161. while (block <= lastblock) {
  162. if (!nand_is_bad_block(block)) {
  163. /*
  164. * Skip bad blocks
  165. */
  166. while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
  167. nand_read_page(block, page, dst);
  168. dst += CONFIG_SYS_NAND_PAGE_SIZE;
  169. page++;
  170. }
  171. page = 0;
  172. } else {
  173. lastblock++;
  174. }
  175. block++;
  176. }
  177. return 0;
  178. }
  179. /* nand_init() - initialize data to make nand usable by SPL */
  180. void nand_init(void)
  181. {
  182. /*
  183. * Init board specific nand support
  184. */
  185. mtd.priv = &nand_chip;
  186. nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
  187. (void __iomem *)CONFIG_SYS_NAND_BASE;
  188. board_nand_init(&nand_chip);
  189. if (nand_chip.select_chip)
  190. nand_chip.select_chip(&mtd, 0);
  191. /* NAND chip may require reset after power-on */
  192. nand_command(0, 0, 0, NAND_CMD_RESET);
  193. }
  194. /* Unselect after operation */
  195. void nand_deselect(void)
  196. {
  197. if (nand_chip.select_chip)
  198. nand_chip.select_chip(&mtd, -1);
  199. }