reset.c 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596
  1. /*
  2. * reset.c - logic for resetting the cpu
  3. *
  4. * Copyright (c) 2005-2008 Analog Devices Inc.
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <asm/blackfin.h>
  11. #include "cpu.h"
  12. /* A system soft reset makes external memory unusable so force
  13. * this function into L1. We use the compiler ssync here rather
  14. * than SSYNC() because it's safe (no interrupts and such) and
  15. * we save some L1. We do not need to force sanity in the SYSCR
  16. * register as the BMODE selection bit is cleared by the soft
  17. * reset while the Core B bit (on dual core parts) is cleared by
  18. * the core reset.
  19. */
  20. __attribute__ ((__l1_text__, __noreturn__))
  21. void bfin_reset(void)
  22. {
  23. /* Wait for completion of "system" events such as cache line
  24. * line fills so that we avoid infinite stalls later on as
  25. * much as possible. This code is in L1, so it won't trigger
  26. * any such event after this point in time.
  27. */
  28. __builtin_bfin_ssync();
  29. while (1) {
  30. /* Initiate System software reset. */
  31. bfin_write_SWRST(0x7);
  32. /* Due to the way reset is handled in the hardware, we need
  33. * to delay for 7 SCLKS. The only reliable way to do this is
  34. * to calculate the CCLK/SCLK ratio and multiply 7. For now,
  35. * we'll assume worse case which is a 1:15 ratio.
  36. */
  37. asm(
  38. "LSETUP (1f, 1f) LC0 = %0\n"
  39. "1: nop;"
  40. :
  41. : "a" (15 * 7)
  42. : "LC0", "LB0", "LT0"
  43. );
  44. /* Clear System software reset */
  45. bfin_write_SWRST(0);
  46. /* Wait for the SWRST write to complete. Cannot rely on SSYNC
  47. * though as the System state is all reset now.
  48. */
  49. asm(
  50. "LSETUP (1f, 1f) LC1 = %0\n"
  51. "1: nop;"
  52. :
  53. : "a" (15 * 1)
  54. : "LC1", "LB1", "LT1"
  55. );
  56. /* Issue core reset */
  57. asm("raise 1");
  58. }
  59. }
  60. /* We need to trampoline ourselves up into L1 since our linker
  61. * does not have relaxtion support and will only generate a
  62. * PC relative call with a 25 bit immediate. This is not enough
  63. * to get us from the top of SDRAM into L1.
  64. */
  65. __attribute__ ((__noreturn__))
  66. static inline void bfin_reset_trampoline(void)
  67. {
  68. if (board_reset)
  69. board_reset();
  70. while (1)
  71. asm("jump (%0);" : : "a" (bfin_reset));
  72. }
  73. __attribute__ ((__noreturn__))
  74. void bfin_reset_or_hang(void)
  75. {
  76. #ifdef CONFIG_PANIC_HANG
  77. hang();
  78. #else
  79. bfin_reset_trampoline();
  80. #endif
  81. }
  82. int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  83. {
  84. bfin_reset_trampoline();
  85. return 0;
  86. }