serial_tegra2.c 2.3 KB

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  1. /*
  2. * (C) Copyright 2010,2011
  3. * NVIDIA Corporation <www.nvidia.com>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <ns16550.h>
  25. #include <asm/io.h>
  26. #include <asm/arch/tegra2.h>
  27. #include "serial_tegra2.h"
  28. static void setup_uart(struct uart_ctlr *u)
  29. {
  30. u32 reg;
  31. /* Prepare the divisor value */
  32. reg = NVRM_PLLP_FIXED_FREQ_KHZ * 1000 / NV_DEFAULT_DEBUG_BAUD / 16;
  33. /* Set up UART parameters */
  34. writel(UART_LCR_DLAB, &u->uart_lcr);
  35. writel(reg, &u->uart_thr_dlab_0);
  36. writel(0, &u->uart_ier_dlab_0);
  37. writel(0, &u->uart_lcr); /* clear DLAB */
  38. writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN | \
  39. UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR), &u->uart_iir_fcr);
  40. writel(0, &u->uart_ier_dlab_0);
  41. writel(UART_LCR_WLS_8, &u->uart_lcr); /* 8N1 */
  42. writel(UART_MCR_RTS, &u->uart_mcr);
  43. writel(0, &u->uart_msr);
  44. writel(0, &u->uart_spr);
  45. writel(0, &u->uart_irda_csr);
  46. writel(0, &u->uart_asr);
  47. writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN), &u->uart_iir_fcr);
  48. /* Flush any old characters out of the RX FIFO */
  49. reg = readl(&u->uart_lsr);
  50. while (reg & UART_LSR_DR) {
  51. reg = readl(&u->uart_thr_dlab_0);
  52. reg = readl(&u->uart_lsr);
  53. }
  54. }
  55. /*
  56. * Routine: uart_init
  57. * Description: init the UART clocks, muxes, and baudrate/parity/etc.
  58. */
  59. void uart_init(void)
  60. {
  61. struct uart_ctlr *uart = (struct uart_ctlr *)NV_PA_APB_UARTD_BASE;
  62. #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
  63. setup_uart(uart);
  64. #endif /* CONFIG_TEGRA2_ENABLE_UARTD */
  65. #if defined(CONFIG_TEGRA2_ENABLE_UARTA)
  66. uart = (struct uart_ctlr *)NV_PA_APB_UARTA_BASE;
  67. setup_uart(uart);
  68. #endif /* CONFIG_TEGRA2_ENABLE_UARTA */
  69. }