pdnb3.c 5.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236
  1. /*
  2. * (C) Copyright 2006
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <command.h>
  25. #include <malloc.h>
  26. #include <asm/arch/ixp425.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. /* predefine these here for FPGA programming (before including fpga.c) */
  29. #define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data)
  30. #define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
  31. #define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
  32. #define OLD_VAL old_val
  33. static unsigned long old_val = 0;
  34. /*
  35. * include common fpga code (for prodrive boards)
  36. */
  37. #include "../common/fpga.c"
  38. /*
  39. * Miscelaneous platform dependent initialisations
  40. */
  41. int board_init(void)
  42. {
  43. /* adress of boot parameters */
  44. gd->bd->bi_boot_params = 0x00000100;
  45. GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
  46. GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
  47. GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
  48. GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
  49. /*
  50. * Setup GPIO's for FPGA programming
  51. */
  52. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
  53. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
  54. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
  55. GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
  56. GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
  57. GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
  58. GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
  59. GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
  60. /*
  61. * Setup GPIO's for interrupts
  62. */
  63. GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
  64. GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
  65. GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
  66. GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
  67. GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
  68. GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
  69. GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
  70. GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
  71. /*
  72. * Setup GPIO's for 33MHz clock output
  73. */
  74. *IXP425_GPIO_GPCLKR = 0x01FF0000;
  75. GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
  76. /*
  77. * Setup other chip select's
  78. */
  79. *IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
  80. return 0;
  81. }
  82. /*
  83. * Check Board Identity
  84. */
  85. int checkboard(void)
  86. {
  87. char buf[64];
  88. int i = getenv_f("serial#", buf, sizeof(buf));
  89. puts("Board: PDNB3");
  90. if (i > 0) {
  91. puts(", serial# ");
  92. puts(buf);
  93. }
  94. putc('\n');
  95. return (0);
  96. }
  97. int dram_init(void)
  98. {
  99. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  100. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  101. return (0);
  102. }
  103. int do_fpga_boot(unsigned char *fpgadata)
  104. {
  105. unsigned char *dst;
  106. int status;
  107. int index;
  108. int i;
  109. ulong len = CONFIG_SYS_MALLOC_LEN;
  110. /*
  111. * Setup GPIO's for FPGA programming
  112. */
  113. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
  114. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
  115. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
  116. /*
  117. * Save value so no readback is required upon programming
  118. */
  119. old_val = *IXP425_GPIO_GPOUTR;
  120. /*
  121. * First try to decompress fpga image (gzip compressed?)
  122. */
  123. dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
  124. if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
  125. printf("Error: Image has to be gzipp'ed!\n");
  126. return -1;
  127. }
  128. status = fpga_boot(dst, len);
  129. if (status != 0) {
  130. printf("\nFPGA: Booting failed ");
  131. switch (status) {
  132. case ERROR_FPGA_PRG_INIT_LOW:
  133. printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
  134. break;
  135. case ERROR_FPGA_PRG_INIT_HIGH:
  136. printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
  137. break;
  138. case ERROR_FPGA_PRG_DONE:
  139. printf("(Timeout: DONE not high after programming FPGA)\n ");
  140. break;
  141. }
  142. /* display infos on fpgaimage */
  143. index = 15;
  144. for (i=0; i<4; i++) {
  145. len = dst[index];
  146. printf("FPGA: %s\n", &(dst[index+1]));
  147. index += len+3;
  148. }
  149. putc ('\n');
  150. /* delayed reboot */
  151. for (i=5; i>0; i--) {
  152. printf("Rebooting in %2d seconds \r",i);
  153. for (index=0;index<1000;index++)
  154. udelay(1000);
  155. }
  156. putc('\n');
  157. do_reset(NULL, 0, 0, NULL);
  158. }
  159. puts("FPGA: ");
  160. /* display infos on fpgaimage */
  161. index = 15;
  162. for (i=0; i<4; i++) {
  163. len = dst[index];
  164. printf("%s ", &(dst[index+1]));
  165. index += len+3;
  166. }
  167. putc('\n');
  168. free(dst);
  169. /*
  170. * Reset FPGA
  171. */
  172. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
  173. udelay(10);
  174. GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
  175. return (0);
  176. }
  177. int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  178. {
  179. ulong addr;
  180. if (argc < 2)
  181. return cmd_usage(cmdtp);
  182. addr = simple_strtoul(argv[1], NULL, 16);
  183. return do_fpga_boot((unsigned char *)addr);
  184. }
  185. U_BOOT_CMD(
  186. fpga, 2, 0, do_fpga,
  187. "boot FPGA",
  188. "address size\n - boot FPGA with gzipped image at <address>"
  189. );
  190. #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
  191. extern struct pci_controller hose;
  192. extern void pci_ixp_init(struct pci_controller * hose);
  193. void pci_init_board(void)
  194. {
  195. extern void pci_ixp_init (struct pci_controller *hose);
  196. pci_ixp_init(&hose);
  197. }
  198. #endif