Эхлэл Бүгдийг харах Тусламж
Бүртгүүлэх Нэвтрэх
phyus
/
uboot-vybrid_public
8
0
Салаа 0
Файлууд Асуудлууд 0 Хуулах хүсэлтүүд 0 Мэдлэгийн сан
Мод: 8cbb0ddd7e
Салаанууд Тагууд
uboot-vybrid_pu...
/
board
/
altera
/
nios2-generic
/
custom_fpga.h

custom_fpga.h 2.1 KB
Түүх Анхны өгөгдөл

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566 
  1. /*
    2. 

  2.  * (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
    3. 

  3.  *
    4. 

  4.  * This program is free software; you can redistribute it and/or modify
    5. 

  5.  * it under the terms of the GNU General Public License version 2 as
    6. 

  6.  * published by the Free Software Foundation.
    7. 

  7.  *
    8. 

  8.  * This file is generated by sopc-create-config-files.
    9. 

  9.  */
    10. 

  10. #ifndef _CUSTOM_FPGA_H_
    11. 

  11. #define _CUSTOM_FPGA_H_
    12. 

  12. 

  13. /* generated from std_1c20.sopc */
    14. 

  14. 

  15. /* cpu.data_master is a altera_nios2 */
    16. 

  16. #define CONFIG_SYS_CLK_FREQ 50000000
    17. 

  17. #define CONFIG_SYS_RESET_ADDR 0x00000000
    18. 

  18. #define CONFIG_SYS_EXCEPTION_ADDR 0x01000020
    19. 

  19. #define CONFIG_SYS_ICACHE_SIZE 4096
    20. 

  20. #define CONFIG_SYS_ICACHELINE_SIZE 32
    21. 

  21. #define CONFIG_SYS_DCACHE_SIZE 2048
    22. 

  22. #define CONFIG_SYS_DCACHELINE_SIZE 4
    23. 

  23. 

  24. /* sdram.s1 is a altera_avalon_new_sdram_controller */
    25. 

  25. #define CONFIG_SYS_SDRAM_BASE 0x01000000
    26. 

  26. #define CONFIG_SYS_SDRAM_SIZE 0x01000000
    27. 

  27. 

  28. /* uart1.s1 is a altera_avalon_uart */
    29. 

  29. #define CONFIG_SYS_UART_BASE 0x82120840
    30. 

  30. #define CONFIG_SYS_UART_FREQ 50000000
    31. 

  31. #define CONFIG_SYS_UART_BAUD 115200
    32. 

  32. 

  33. /* lan91c111.s1 is a altera_avalon_lan91c111 */
    34. 

  34. #define CONFIG_SMC91111_BASE 0x82110300
    35. 

  35. #define CONFIG_SMC91111
    36. 

  36. #define CONFIG_SMC_USE_32_BIT
    37. 

  37. 

  38. /* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
    39. 

  39. #define CONFIG_SYS_JTAG_UART_BASE 0x821208b0
    40. 

  40. 

  41. /* led_pio.s1 is a altera_avalon_pio */
    42. 

  42. #define LED_PIO_BASE 0x82120870
    43. 

  43. 

  44. /* high_res_timer.s1 is a altera_avalon_timer */
    45. 

  45. #define CONFIG_SYS_TIMER_BASE 0x82120820
    46. 

  46. #define CONFIG_SYS_TIMER_IRQ 3
    47. 

  47. #define CONFIG_SYS_TIMER_FREQ 50000000
    48. 

  48. 

  49. /* ext_flash.s1 is a altera_avalon_cfi_flash */
    50. 

  50. #define CONFIG_SYS_FLASH_BASE 0x80000000
    51. 

  51. #define CONFIG_FLASH_CFI_DRIVER
    52. 

  52. #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
    53. 

  53. #define CONFIG_SYS_FLASH_CFI
    54. 

  54. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
    55. 

  55. #define CONFIG_SYS_FLASH_PROTECTION
    56. 

  56. #define CONFIG_SYS_MAX_FLASH_BANKS 1
    57. 

  57. #define CONFIG_SYS_MAX_FLASH_SECT 1024
    58. 

  58. 

  59. /* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */
    60. 

  60. #define CONFIG_SYS_SRAM_BASE 0x02000000
    61. 

  61. #define CONFIG_SYS_SRAM_SIZE 0x00100000
    62. 

  62. 

  63. /* sysid.control_slave is a altera_avalon_sysid */
    64. 

  64. #define CONFIG_SYS_SYSID_BASE 0x821208b8
    65. 

  65. 

  66. #endif /* _CUSTOM_FPGA_H_ */
    67.