pb1x00.h 5.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213
  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * This file contains the configuration parameters for the dbau1x00 board.
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. #define CONFIG_MIPS32 1 /* MIPS32 CPU core */
  29. #define CONFIG_PB1X00 1
  30. #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
  31. #ifdef CONFIG_PB1000
  32. #define CONFIG_SOC_AU1000 1
  33. #else
  34. #ifdef CONFIG_PB1100
  35. #define CONFIG_SOC_AU1100 1
  36. #else
  37. #ifdef CONFIG_PB1500
  38. #define CONFIG_SOC_AU1500 1
  39. #else
  40. #error "No valid board set"
  41. #endif
  42. #endif
  43. #endif
  44. #define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
  45. #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
  46. #define CONFIG_BAUDRATE 115200
  47. /* valid baudrates */
  48. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  49. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  50. #undef CONFIG_BOOTARGS
  51. #define CONFIG_EXTRA_ENV_SETTINGS \
  52. "addmisc=setenv bootargs ${bootargs} " \
  53. "console=ttyS0,${baudrate} " \
  54. "panic=1\0" \
  55. "bootfile=/vmlinux.img\0" \
  56. "load=tftp 80500000 ${u-boot}\0" \
  57. ""
  58. /* Boot from NFS root */
  59. #define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm"
  60. /*
  61. * Miscellaneous configurable options
  62. */
  63. #define CFG_LONGHELP /* undef to save memory */
  64. #define CFG_PROMPT "Pb1x00 # " /* Monitor Command Prompt */
  65. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  66. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  67. #define CFG_MAXARGS 16 /* max number of command args*/
  68. #define CFG_MALLOC_LEN 128*1024
  69. #define CFG_BOOTPARAMS_LEN 128*1024
  70. #define CFG_MIPS_TIMER_FREQ 396000000
  71. #define CFG_HZ 1000
  72. #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
  73. #define CFG_LOAD_ADDR 0x81000000 /* default load address */
  74. #define CFG_MEMTEST_START 0x80100000
  75. #undef CFG_MEMTEST_START
  76. #define CFG_MEMTEST_START 0x80200000
  77. #define CFG_MEMTEST_END 0x83800000
  78. /*-----------------------------------------------------------------------
  79. * FLASH and environment organization
  80. */
  81. #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  82. #define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
  83. #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
  84. #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
  85. /* The following #defines are needed to get flash environment right */
  86. #define CFG_MONITOR_BASE TEXT_BASE
  87. #define CFG_MONITOR_LEN (192 << 10)
  88. #define CFG_INIT_SP_OFFSET 0x4000000
  89. /* We boot from this flash, selected with dip switch */
  90. #define CFG_FLASH_BASE PHYS_FLASH_2
  91. /* timeout values are in ticks */
  92. #define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
  93. #define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
  94. #define CFG_ENV_IS_NOWHERE 1
  95. /* Address and size of Primary Environment Sector */
  96. #define CFG_ENV_ADDR 0xB0030000
  97. #define CFG_ENV_SIZE 0x10000
  98. #define CONFIG_FLASH_16BIT
  99. #define CONFIG_NR_DRAM_BANKS 2
  100. #define CONFIG_NET_MULTI
  101. #define CONFIG_MEMSIZE_IN_BYTES
  102. /*---USB -------------------------------------------*/
  103. #if 0
  104. #define CONFIG_USB_OHCI
  105. #define CONFIG_USB_STORAGE
  106. #define CONFIG_DOS_PARTITION
  107. #endif
  108. /*---ATA PCMCIA ------------------------------------*/
  109. #if 0
  110. #define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
  111. #define CFG_PCMCIA_MEM_ADDR 0x20000000
  112. #define CONFIG_PCMCIA_SLOT_A
  113. #define CONFIG_ATAPI 1
  114. #define CONFIG_MAC_PARTITION 1
  115. /* We run CF in "true ide" mode or a harddrive via pcmcia */
  116. #define CONFIG_IDE_PCMCIA 1
  117. /* We only support one slot for now */
  118. #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
  119. #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  120. #undef CONFIG_IDE_LED /* LED for ide not supported */
  121. #undef CONFIG_IDE_RESET /* reset for ide not supported */
  122. #define CFG_ATA_IDE0_OFFSET 0x0000
  123. #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
  124. /* Offset for data I/O */
  125. #define CFG_ATA_DATA_OFFSET 8
  126. /* Offset for normal register accesses */
  127. #define CFG_ATA_REG_OFFSET 0
  128. /* Offset for alternate registers */
  129. #define CFG_ATA_ALT_OFFSET 0x0100
  130. #endif
  131. /*-----------------------------------------------------------------------
  132. * Cache Configuration
  133. */
  134. #define CFG_DCACHE_SIZE 16384
  135. #define CFG_ICACHE_SIZE 16384
  136. #define CFG_CACHELINE_SIZE 32
  137. /*
  138. * BOOTP options
  139. */
  140. #define CONFIG_BOOTP_BOOTFILESIZE
  141. #define CONFIG_BOOTP_BOOTPATH
  142. #define CONFIG_BOOTP_GATEWAY
  143. #define CONFIG_BOOTP_HOSTNAME
  144. /*
  145. * Command line configuration.
  146. */
  147. #include <config_cmd_default.h>
  148. #define CONFIG_CMD_DHCP
  149. #define CONFIG_CMD_ELF
  150. #define CONFIG_CMD_MII
  151. #define CONFIG_CMD_PING
  152. #undef CONFIG_CMD_ENV
  153. #undef CONFIG_CMD_FAT
  154. #undef CONFIG_CMD_FLASH
  155. #undef CONFIG_CMD_FPGA
  156. #undef CONFIG_CMD_IDE
  157. #undef CONFIG_CMD_LOADS
  158. #undef CONFIG_CMD_RUN
  159. #undef CONFIG_CMD_LOADB
  160. #undef CONFIG_CMD_ELF
  161. #undef CONFIG_CMD_BDI
  162. #undef CONFIG_CMD_BEDBUG
  163. #endif /* __CONFIG_H */