max77686_pmic.h 5.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190
  1. /*
  2. * Copyright (C) 2012 Samsung Electronics
  3. * Rajeshwari Shinde <rajeshwari.s@samsung.com>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef __MAX77686_H_
  24. #define __MAX77686_H_
  25. enum {
  26. MAX77686_REG_PMIC_ID = 0x0,
  27. MAX77686_REG_PMIC_INTSRC,
  28. MAX77686_REG_PMIC_INT1,
  29. MAX77686_REG_PMIC_INT2,
  30. MAX77686_REG_PMIC_INT1MSK,
  31. MAX77686_REG_PMIC_INT2MSK,
  32. MAX77686_REG_PMIC_STATUS1,
  33. MAX77686_REG_PMIC_STATUS2,
  34. MAX77686_REG_PMIC_PWRON,
  35. MAX77686_REG_PMIC_ONOFFDELAY,
  36. MAX77686_REG_PMIC_MRSTB,
  37. MAX77686_REG_PMIC_BUCK1CRTL = 0x10,
  38. MAX77686_REG_PMIC_BUCK1OUT,
  39. MAX77686_REG_PMIC_BUCK2CTRL1,
  40. MAX77686_REG_PMIC_BUCK234FREQ,
  41. MAX77686_REG_PMIC_BUCK2DVS1,
  42. MAX77686_REG_PMIC_BUCK2DVS2,
  43. MAX77686_REG_PMIC_BUCK2DVS3,
  44. MAX77686_REG_PMIC_BUCK2DVS4,
  45. MAX77686_REG_PMIC_BUCK2DVS5,
  46. MAX77686_REG_PMIC_BUCK2DVS6,
  47. MAX77686_REG_PMIC_BUCK2DVS7,
  48. MAX77686_REG_PMIC_BUCK2DVS8,
  49. MAX77686_REG_PMIC_BUCK3CTRL,
  50. MAX77686_REG_PMIC_BUCK3DVS1,
  51. MAX77686_REG_PMIC_BUCK3DVS2,
  52. MAX77686_REG_PMIC_BUCK3DVS3,
  53. MAX77686_REG_PMIC_BUCK3DVS4,
  54. MAX77686_REG_PMIC_BUCK3DVS5,
  55. MAX77686_REG_PMIC_BUCK3DVS6,
  56. MAX77686_REG_PMIC_BUCK3DVS7,
  57. MAX77686_REG_PMIC_BUCK3DVS8,
  58. MAX77686_REG_PMIC_BUCK4CTRL1,
  59. MAX77686_REG_PMIC_BUCK4DVS1 = 0x28,
  60. MAX77686_REG_PMIC_BUCK4DVS2,
  61. MAX77686_REG_PMIC_BUCK4DVS3,
  62. MAX77686_REG_PMIC_BUCK4DVS4,
  63. MAX77686_REG_PMIC_BUCK4DVS5,
  64. MAX77686_REG_PMIC_BUCK4DVS6,
  65. MAX77686_REG_PMIC_BUCK4DVS7,
  66. MAX77686_REG_PMIC_BUCK4DVS8,
  67. MAX77686_REG_PMIC_BUCK5CTRL,
  68. MAX77686_REG_PMIC_BUCK5OUT,
  69. MAX77686_REG_PMIC_BUCK6CRTL,
  70. MAX77686_REG_PMIC_BUCK6OUT,
  71. MAX77686_REG_PMIC_BUCK7CRTL,
  72. MAX77686_REG_PMIC_BUCK7OUT,
  73. MAX77686_REG_PMIC_BUCK8CRTL,
  74. MAX77686_REG_PMIC_BUCK8OUT,
  75. MAX77686_REG_PMIC_BUCK9CRTL,
  76. MAX77686_REG_PMIC_BUCK9OUT,
  77. MAX77686_REG_PMIC_LDO1CTRL1 = 0x40,
  78. MAX77686_REG_PMIC_LDO2CTRL1,
  79. MAX77686_REG_PMIC_LDO3CTRL1,
  80. MAX77686_REG_PMIC_LDO4CTRL1,
  81. MAX77686_REG_PMIC_LDO5CTRL1,
  82. MAX77686_REG_PMIC_LDO6CTRL1,
  83. MAX77686_REG_PMIC_LDO7CTRL1,
  84. MAX77686_REG_PMIC_LDO8CTRL1,
  85. MAX77686_REG_PMIC_LDO9CTRL1,
  86. MAX77686_REG_PMIC_LDO10CTRL1,
  87. MAX77686_REG_PMIC_LDO11CTRL1,
  88. MAX77686_REG_PMIC_LDO12CTRL1,
  89. MAX77686_REG_PMIC_LDO13CTRL1,
  90. MAX77686_REG_PMIC_LDO14CTRL1,
  91. MAX77686_REG_PMIC_LDO15CTRL1,
  92. MAX77686_REG_PMIC_LDO16CTRL1,
  93. MAX77686_REG_PMIC_LDO17CTRL1,
  94. MAX77686_REG_PMIC_LDO18CTRL1,
  95. MAX77686_REG_PMIC_LDO19CTRL1,
  96. MAX77686_REG_PMIC_LDO20CTRL1,
  97. MAX77686_REG_PMIC_LDO21CTRL1,
  98. MAX77686_REG_PMIC_LDO22CTRL1,
  99. MAX77686_REG_PMIC_LDO23CTRL1,
  100. MAX77686_REG_PMIC_LDO24CTRL1,
  101. MAX77686_REG_PMIC_LDO25CTRL1,
  102. MAX77686_REG_PMIC_LDO26CTRL1,
  103. MAX77686_REG_PMIC_LDO1CTRL2,
  104. MAX77686_REG_PMIC_LDO2CTRL2,
  105. MAX77686_REG_PMIC_LDO3CTRL2,
  106. MAX77686_REG_PMIC_LDO4CTRL2,
  107. MAX77686_REG_PMIC_LDO5CTRL2,
  108. MAX77686_REG_PMIC_LDO6CTRL2,
  109. MAX77686_REG_PMIC_LDO7CTRL2,
  110. MAX77686_REG_PMIC_LDO8CTRL2,
  111. MAX77686_REG_PMIC_LDO9CTRL2,
  112. MAX77686_REG_PMIC_LDO10CTRL2,
  113. MAX77686_REG_PMIC_LDO11CTRL2,
  114. MAX77686_REG_PMIC_LDO12CTRL2,
  115. MAX77686_REG_PMIC_LDO13CTRL2,
  116. MAX77686_REG_PMIC_LDO14CTRL2,
  117. MAX77686_REG_PMIC_LDO15CTRL2,
  118. MAX77686_REG_PMIC_LDO16CTRL2,
  119. MAX77686_REG_PMIC_LDO17CTRL2,
  120. MAX77686_REG_PMIC_LDO18CTRL2,
  121. MAX77686_REG_PMIC_LDO19CTRL2,
  122. MAX77686_REG_PMIC_LDO20CTRL2,
  123. MAX77686_REG_PMIC_LDO21CTRL2,
  124. MAX77686_REG_PMIC_LDO22CTRL2,
  125. MAX77686_REG_PMIC_LDO23CTRL2,
  126. MAX77686_REG_PMIC_LDO24CTRL2,
  127. MAX77686_REG_PMIC_LDO25CTRL2,
  128. MAX77686_REG_PMIC_LDO26CTRL2,
  129. MAX77686_REG_PMIC_BBAT = 0x7e,
  130. MAX77686_REG_PMIC_32KHZ,
  131. PMIC_NUM_OF_REGS,
  132. };
  133. /* I2C device address for pmic max77686 */
  134. #define MAX77686_I2C_ADDR (0x12 >> 1)
  135. enum {
  136. REG_DISABLE = 0,
  137. REG_ENABLE
  138. };
  139. enum {
  140. LDO_OFF = 0,
  141. LDO_ON,
  142. DIS_LDO = (0x00 << 6),
  143. EN_LDO = (0x3 << 6),
  144. };
  145. /* Buck1 1 volt value */
  146. #define MAX77686_BUCK1OUT_1V 0x5
  147. #define MAX77686_BUCK1CTRL_EN (3 << 0)
  148. /* Buck2 1.3 volt value */
  149. #define MAX77686_BUCK2DVS1_1_3V 0x38
  150. #define MAX77686_BUCK2CTRL_ON (1 << 4)
  151. /* Buck3 1.0125 volt value */
  152. #define MAX77686_BUCK3DVS1_1_0125V 0x21
  153. #define MAX77686_BUCK3CTRL_ON (1 << 4)
  154. /* Buck4 1.2 volt value */
  155. #define MAX77686_BUCK4DVS1_1_2V 0x30
  156. #define MAX77686_BUCK4CTRL_ON (1 << 4)
  157. /* LDO2 1.5 volt value */
  158. #define MAX77686_LD02CTRL1_1_5V 0x1c
  159. /* LDO3 1.8 volt value */
  160. #define MAX77686_LD03CTRL1_1_8V 0x14
  161. /* LDO5 1.8 volt value */
  162. #define MAX77686_LD05CTRL1_1_8V 0x14
  163. /* LDO10 1.8 volt value */
  164. #define MAX77686_LD10CTRL1_1_8V 0x14
  165. /*
  166. * MAX77686_REG_PMIC_32KHZ set to 32KH CP
  167. * output is activated
  168. */
  169. #define MAX77686_32KHCP_EN (1 << 1)
  170. /*
  171. * MAX77686_REG_PMIC_BBAT set to
  172. * Back up batery charger on and
  173. * limit voltage setting to 3.5v
  174. */
  175. #define MAX77686_BBCHOSTEN (1 << 0)
  176. #define MAX77686_BBCVS_3_5V (3 << 3)
  177. #endif /* __MAX77686_PMIC_H_ */