fpga.c 3.9 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  4. * Keith Outwater, keith_outwater@mvis.com.
  5. *
  6. * (C) Copyright 2008
  7. * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. *
  27. */
  28. #include <common.h>
  29. #include <ACEX1K.h>
  30. #include <command.h>
  31. #include "fpga.h"
  32. #include "mvblm7.h"
  33. #ifdef FPGA_DEBUG
  34. #define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
  35. #else
  36. #define fpga_debug(fmt, args...)
  37. #endif
  38. Altera_CYC2_Passive_Serial_fns altera_fns = {
  39. fpga_null_fn,
  40. fpga_config_fn,
  41. fpga_status_fn,
  42. fpga_done_fn,
  43. fpga_wr_fn,
  44. fpga_null_fn,
  45. fpga_null_fn,
  46. };
  47. Altera_desc cyclone2 = {
  48. Altera_CYC2,
  49. passive_serial,
  50. Altera_EP2C20_SIZE,
  51. (void *) &altera_fns,
  52. NULL,
  53. 0
  54. };
  55. DECLARE_GLOBAL_DATA_PTR;
  56. int mvblm7_init_fpga(void)
  57. {
  58. fpga_debug("Initialize FPGA interface\n");
  59. fpga_init();
  60. fpga_add(fpga_altera, &cyclone2);
  61. fpga_config_fn(0, 1, 0);
  62. udelay(60);
  63. return 1;
  64. }
  65. int fpga_null_fn(int cookie)
  66. {
  67. return 0;
  68. }
  69. int fpga_config_fn(int assert, int flush, int cookie)
  70. {
  71. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  72. volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
  73. u32 dvo = gpio->dat;
  74. fpga_debug("SET config : %s\n", assert ? "low" : "high");
  75. if (assert)
  76. dvo |= FPGA_CONFIG;
  77. else
  78. dvo &= ~FPGA_CONFIG;
  79. if (flush)
  80. gpio->dat = dvo;
  81. return assert;
  82. }
  83. int fpga_done_fn(int cookie)
  84. {
  85. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  86. volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
  87. int result = 0;
  88. udelay(10);
  89. fpga_debug("CONF_DONE check ... ");
  90. if (gpio->dat & FPGA_CONF_DONE) {
  91. fpga_debug("high\n");
  92. result = 1;
  93. } else
  94. fpga_debug("low\n");
  95. return result;
  96. }
  97. int fpga_status_fn(int cookie)
  98. {
  99. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  100. volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
  101. int result = 0;
  102. fpga_debug("STATUS check ... ");
  103. if (gpio->dat & FPGA_STATUS) {
  104. fpga_debug("high\n");
  105. result = 1;
  106. } else
  107. fpga_debug("low\n");
  108. return result;
  109. }
  110. int fpga_clk_fn(int assert_clk, int flush, int cookie)
  111. {
  112. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  113. volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
  114. u32 dvo = gpio->dat;
  115. fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
  116. if (assert_clk)
  117. dvo |= FPGA_CCLK;
  118. else
  119. dvo &= ~FPGA_CCLK;
  120. if (flush)
  121. gpio->dat = dvo;
  122. return assert_clk;
  123. }
  124. static inline int _write_fpga(u8 val, int dump)
  125. {
  126. volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  127. volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
  128. int i;
  129. u32 dvo = gpio->dat;
  130. if (dump)
  131. fpga_debug(" %02x -> ", val);
  132. for (i = 0; i < 8; i++) {
  133. dvo &= ~FPGA_CCLK;
  134. gpio->dat = dvo;
  135. dvo &= ~FPGA_DIN;
  136. if (dump)
  137. fpga_debug("%d ", val&1);
  138. if (val & 1)
  139. dvo |= FPGA_DIN;
  140. gpio->dat = dvo;
  141. dvo |= FPGA_CCLK;
  142. gpio->dat = dvo;
  143. val >>= 1;
  144. }
  145. if (dump)
  146. fpga_debug("\n");
  147. return 0;
  148. }
  149. int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
  150. {
  151. unsigned char *data = (unsigned char *) buf;
  152. int i;
  153. fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
  154. for (i = 0; i < len; i++)
  155. _write_fpga(data[i], 0);
  156. fpga_debug("\n");
  157. return FPGA_SUCCESS;
  158. }