at91sam9263ek.c 8.0 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stelian Pop <stelian@popies.net>
  4. * Lead Tech Design <www.leadtechdesign.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <common.h>
  25. #include <asm/sizes.h>
  26. #include <asm/arch/at91sam9263.h>
  27. #include <asm/arch/at91sam9_smc.h>
  28. #include <asm/arch/at91_common.h>
  29. #include <asm/arch/at91_pmc.h>
  30. #include <asm/arch/at91_rstc.h>
  31. #include <asm/arch/at91_matrix.h>
  32. #include <asm/arch/at91_pio.h>
  33. #include <asm/arch/clk.h>
  34. #include <asm/io.h>
  35. #include <asm/arch/gpio.h>
  36. #include <asm/arch/hardware.h>
  37. #include <lcd.h>
  38. #include <atmel_lcdc.h>
  39. #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  40. #include <net.h>
  41. #endif
  42. #include <netdev.h>
  43. DECLARE_GLOBAL_DATA_PTR;
  44. /* ------------------------------------------------------------------------- */
  45. /*
  46. * Miscelaneous platform dependent initialisations
  47. */
  48. #ifdef CONFIG_CMD_NAND
  49. static void at91sam9263ek_nand_hw_init(void)
  50. {
  51. unsigned long csa;
  52. at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
  53. at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  54. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  55. /* Enable CS3 */
  56. csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  57. writel(csa, &matrix->csa[0]);
  58. /* Enable CS3 */
  59. /* Configure SMC CS3 for NAND/SmartMedia */
  60. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  61. AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  62. &smc->cs[3].setup);
  63. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  64. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  65. &smc->cs[3].pulse);
  66. writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  67. &smc->cs[3].cycle);
  68. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  69. AT91_SMC_MODE_EXNW_DISABLE |
  70. #ifdef CONFIG_SYS_NAND_DBW_16
  71. AT91_SMC_MODE_DBW_16 |
  72. #else /* CONFIG_SYS_NAND_DBW_8 */
  73. AT91_SMC_MODE_DBW_8 |
  74. #endif
  75. AT91_SMC_MODE_TDF_CYCLE(2),
  76. &smc->cs[3].mode);
  77. writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE,
  78. &pmc->pcer);
  79. /* Configure RDY/BSY */
  80. at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  81. /* Enable NandFlash */
  82. at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  83. }
  84. #endif
  85. #ifdef CONFIG_MACB
  86. static void at91sam9263ek_macb_hw_init(void)
  87. {
  88. unsigned long erstl;
  89. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  90. at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
  91. at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
  92. /* Enable clock */
  93. writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  94. /*
  95. * Disable pull-up on:
  96. * RXDV (PC25) => PHY normal mode (not Test mode)
  97. * ERX0 (PE25) => PHY ADDR0
  98. * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
  99. *
  100. * PHY has internal pull-down
  101. */
  102. writel(1 << 25, &pio->pioc.pudr);
  103. writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
  104. erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
  105. /* Need to reset PHY -> 500ms reset */
  106. writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
  107. AT91_RSTC_MR_URSTEN, &rstc->mr);
  108. writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
  109. /* Wait for end hardware reset */
  110. while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
  111. ;
  112. /* Restore NRST value */
  113. writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
  114. /* Re-enable pull-up */
  115. writel(1 << 25, &pio->pioc.puer);
  116. writel((1 << 25) | (1 <<26), &pio->pioe.puer);
  117. at91_macb_hw_init();
  118. }
  119. #endif
  120. #ifdef CONFIG_LCD
  121. vidinfo_t panel_info = {
  122. vl_col: 240,
  123. vl_row: 320,
  124. vl_clk: 4965000,
  125. vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
  126. ATMEL_LCDC_INVFRAME_INVERTED,
  127. vl_bpix: 3,
  128. vl_tft: 1,
  129. vl_hsync_len: 5,
  130. vl_left_margin: 1,
  131. vl_right_margin:33,
  132. vl_vsync_len: 1,
  133. vl_upper_margin:1,
  134. vl_lower_margin:0,
  135. mmio: ATMEL_BASE_LCDC,
  136. };
  137. void lcd_enable(void)
  138. {
  139. at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power up */
  140. }
  141. void lcd_disable(void)
  142. {
  143. at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power down */
  144. }
  145. static void at91sam9263ek_lcd_hw_init(void)
  146. {
  147. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  148. at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
  149. at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
  150. at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
  151. at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
  152. at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
  153. at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
  154. at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
  155. at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
  156. at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
  157. at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
  158. at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
  159. at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
  160. at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
  161. at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
  162. at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
  163. at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
  164. at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
  165. at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
  166. at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
  167. at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
  168. at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
  169. at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
  170. writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
  171. gd->fb_base = ATMEL_BASE_SRAM0;
  172. }
  173. #ifdef CONFIG_LCD_INFO
  174. #include <nand.h>
  175. #include <version.h>
  176. #ifndef CONFIG_SYS_NO_FLASH
  177. extern flash_info_t flash_info[];
  178. #endif
  179. void lcd_show_board_info(void)
  180. {
  181. ulong dram_size, nand_size;
  182. #ifndef CONFIG_SYS_NO_FLASH
  183. ulong flash_size;
  184. #endif
  185. int i;
  186. char temp[32];
  187. lcd_printf ("%s\n", U_BOOT_VERSION);
  188. lcd_printf ("(C) 2008 ATMEL Corp\n");
  189. lcd_printf ("at91support@atmel.com\n");
  190. lcd_printf ("%s CPU at %s MHz\n",
  191. ATMEL_CPU_NAME,
  192. strmhz(temp, get_cpu_clk_rate()));
  193. dram_size = 0;
  194. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
  195. dram_size += gd->bd->bi_dram[i].size;
  196. nand_size = 0;
  197. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  198. nand_size += nand_info[i].size;
  199. #ifndef CONFIG_SYS_NO_FLASH
  200. flash_size = 0;
  201. for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
  202. flash_size += flash_info[i].size;
  203. #endif
  204. lcd_printf (" %ld MB SDRAM, %ld MB NAND",
  205. dram_size >> 20,
  206. nand_size >> 20 );
  207. #ifndef CONFIG_SYS_NO_FLASH
  208. lcd_printf (",\n %ld MB NOR",
  209. flash_size >> 20);
  210. #endif
  211. lcd_puts ("\n");
  212. }
  213. #endif /* CONFIG_LCD_INFO */
  214. #endif
  215. int board_early_init_f(void)
  216. {
  217. struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  218. /* Enable clocks for all PIOs */
  219. writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
  220. (1 << ATMEL_ID_PIOCDE),
  221. &pmc->pcer);
  222. at91_seriald_hw_init();
  223. return 0;
  224. }
  225. int board_init(void)
  226. {
  227. /* arch number of AT91SAM9263EK-Board */
  228. gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
  229. /* adress of boot parameters */
  230. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  231. #ifdef CONFIG_CMD_NAND
  232. at91sam9263ek_nand_hw_init();
  233. #endif
  234. #ifdef CONFIG_HAS_DATAFLASH
  235. at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */
  236. at91_spi0_hw_init(1 << 0);
  237. #endif
  238. #ifdef CONFIG_MACB
  239. at91sam9263ek_macb_hw_init();
  240. #endif
  241. #ifdef CONFIG_USB_OHCI_NEW
  242. at91_uhp_hw_init();
  243. #endif
  244. #ifdef CONFIG_LCD
  245. at91sam9263ek_lcd_hw_init();
  246. #endif
  247. return 0;
  248. }
  249. int dram_init(void)
  250. {
  251. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  252. CONFIG_SYS_SDRAM_SIZE);
  253. return 0;
  254. }
  255. #ifdef CONFIG_RESET_PHY_R
  256. void reset_phy(void)
  257. {
  258. }
  259. #endif
  260. int board_eth_init(bd_t *bis)
  261. {
  262. int rc = 0;
  263. #ifdef CONFIG_MACB
  264. rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
  265. #endif
  266. return rc;
  267. }