a320evb.h 6.0 KB

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  1. /*
  2. * (C) Copyright 2009 Faraday Technology
  3. * Po-Yu Chuang <ratbert@faraday-tech.com>
  4. *
  5. * Configuation settings for the Faraday A320 board.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #ifndef __CONFIG_H
  22. #define __CONFIG_H
  23. #include <asm/arch/a320.h>
  24. /*
  25. * Linux kernel tagged list
  26. */
  27. #define CONFIG_CMDLINE_TAG
  28. #define CONFIG_SETUP_MEMORY_TAGS
  29. /*
  30. * CPU and Board Configuration Options
  31. */
  32. #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  33. #undef CONFIG_SKIP_LOWLEVEL_INIT
  34. /*
  35. * Power Management Unit
  36. */
  37. #define CONFIG_FTPMU010_POWER
  38. /*
  39. * Timer
  40. */
  41. #define CONFIG_SYS_HZ 1000 /* timer ticks per second */
  42. /*
  43. * Real Time Clock
  44. */
  45. #define CONFIG_RTC_FTRTC010
  46. /*
  47. * Serial console configuration
  48. */
  49. /* FTUART is a high speed NS 16C550A compatible UART */
  50. #define CONFIG_BAUDRATE 38400
  51. #define CONFIG_CONS_INDEX 1
  52. #define CONFIG_SYS_NS16550
  53. #define CONFIG_SYS_NS16550_SERIAL
  54. #define CONFIG_SYS_NS16550_COM1 0x98200000
  55. #define CONFIG_SYS_NS16550_REG_SIZE -4
  56. #define CONFIG_SYS_NS16550_CLK 18432000
  57. /* valid baudrates */
  58. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  59. /*
  60. * Ethernet
  61. */
  62. #define CONFIG_FTMAC100
  63. #define CONFIG_BOOTDELAY 3
  64. /*
  65. * Command line configuration.
  66. */
  67. #include <config_cmd_default.h>
  68. #define CONFIG_CMD_CACHE
  69. #define CONFIG_CMD_DATE
  70. #define CONFIG_CMD_PING
  71. /*
  72. * Miscellaneous configurable options
  73. */
  74. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  75. #define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
  76. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  77. /* Print Buffer Size */
  78. #define CONFIG_SYS_PBSIZE \
  79. (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  80. /* max number of command args */
  81. #define CONFIG_SYS_MAXARGS 16
  82. /* Boot Argument Buffer Size */
  83. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  84. /*
  85. * Stack sizes
  86. *
  87. * The stack sizes are set up in start.S using the settings below
  88. */
  89. #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
  90. #ifdef CONFIG_USE_IRQ
  91. #define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
  92. #define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
  93. #endif
  94. /*
  95. * Size of malloc() pool
  96. */
  97. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
  98. /*
  99. * SDRAM controller configuration
  100. */
  101. #define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
  102. FTSDMC020_TP0_TRP(1) | \
  103. FTSDMC020_TP0_TRCD(1) | \
  104. FTSDMC020_TP0_TRF(3) | \
  105. FTSDMC020_TP0_TWR(1) | \
  106. FTSDMC020_TP0_TCL(2))
  107. #define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
  108. FTSDMC020_TP1_INI_REFT(8) | \
  109. FTSDMC020_TP1_REF_INTV(0x180))
  110. #define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
  111. FTSDMC020_BANK_DDW_X16 | \
  112. FTSDMC020_BANK_DSZ_256M | \
  113. FTSDMC020_BANK_MBW_32 | \
  114. FTSDMC020_BANK_SIZE_64M)
  115. /*
  116. * Physical Memory Map
  117. */
  118. #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  119. #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
  120. #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
  121. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  122. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
  123. GENERATED_GBL_DATA_SIZE)
  124. /*
  125. * Load address and memory test area should agree with
  126. * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
  127. */
  128. #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000)
  129. /* memtest works on 63 MB in DRAM */
  130. #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
  131. #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000)
  132. #define CONFIG_SYS_TEXT_BASE 0
  133. /*
  134. * Static memory controller configuration
  135. */
  136. #define CONFIG_FTSMC020
  137. #include <faraday/ftsmc020.h>
  138. #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
  139. FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
  140. FTSMC020_BANK_SIZE_1M | \
  141. FTSMC020_BANK_MBW_8)
  142. #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
  143. FTSMC020_TPR_AST(3) | \
  144. FTSMC020_TPR_CTW(3) | \
  145. FTSMC020_TPR_ATI(0xf) | \
  146. FTSMC020_TPR_AT2(3) | \
  147. FTSMC020_TPR_WTC(3) | \
  148. FTSMC020_TPR_AHT(3) | \
  149. FTSMC020_TPR_TRNA(0xf))
  150. #define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
  151. FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
  152. FTSMC020_BANK_SIZE_32M | \
  153. FTSMC020_BANK_MBW_32)
  154. #define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
  155. FTSMC020_TPR_CTW(3) | \
  156. FTSMC020_TPR_ATI(0xf) | \
  157. FTSMC020_TPR_AT2(3) | \
  158. FTSMC020_TPR_WTC(3) | \
  159. FTSMC020_TPR_AHT(3) | \
  160. FTSMC020_TPR_TRNA(0xf))
  161. #define CONFIG_SYS_FTSMC020_CONFIGS { \
  162. { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
  163. { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
  164. }
  165. /*
  166. * FLASH and environment organization
  167. */
  168. /* use CFI framework */
  169. #define CONFIG_SYS_FLASH_CFI
  170. #define CONFIG_FLASH_CFI_DRIVER
  171. /* support JEDEC */
  172. #define CONFIG_FLASH_CFI_LEGACY
  173. #define CONFIG_SYS_FLASH_LEGACY_512Kx8
  174. #define PHYS_FLASH_1 0x00000000
  175. #define PHYS_FLASH_2 0x00400000
  176. #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
  177. #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
  178. #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
  179. /* max number of memory banks */
  180. #define CONFIG_SYS_MAX_FLASH_BANKS 2
  181. /* max number of sectors on one chip */
  182. #define CONFIG_SYS_MAX_FLASH_SECT 512
  183. #undef CONFIG_SYS_FLASH_EMPTY_INFO
  184. /* environments */
  185. #define CONFIG_ENV_IS_IN_FLASH
  186. #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
  187. #define CONFIG_ENV_SIZE 0x20000
  188. #endif /* __CONFIG_H */