MVBC_P.h 8.7 KB

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  1. /*
  2. * (C) Copyright 2003-2004
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2004-2008
  6. * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. #include <version.h>
  29. #define CONFIG_MPC5xxx 1
  30. #define CONFIG_MPC5200 1
  31. #ifndef CONFIG_SYS_TEXT_BASE
  32. #define CONFIG_SYS_TEXT_BASE 0xFF800000
  33. #endif
  34. #define CONFIG_SYS_MPC5XXX_CLKIN 33000000
  35. #define CONFIG_MISC_INIT_R 1
  36. #define CONFIG_SYS_CACHELINE_SIZE 32
  37. #ifdef CONFIG_CMD_KGDB
  38. #define CONFIG_SYS_CACHELINE_SHIFT 5
  39. #endif
  40. #define CONFIG_PSC_CONSOLE 1
  41. #define CONFIG_BAUDRATE 115200
  42. #define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200, 230400}
  43. #define CONFIG_PCI 1
  44. #define CONFIG_PCI_PNP 1
  45. #undef CONFIG_PCI_SCAN_SHOW
  46. #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  47. #define CONFIG_PCI_MEM_BUS 0x40000000
  48. #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
  49. #define CONFIG_PCI_MEM_SIZE 0x10000000
  50. #define CONFIG_PCI_IO_BUS 0x50000000
  51. #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
  52. #define CONFIG_PCI_IO_SIZE 0x01000000
  53. #define CONFIG_SYS_XLB_PIPELINING 1
  54. #define CONFIG_HIGH_BATS 1
  55. #define MV_CI mvBlueCOUGAR-P
  56. #define MV_VCI mvBlueCOUGAR-P
  57. #define MV_FPGA_DATA 0xff860000
  58. #define MV_FPGA_SIZE 0
  59. #define MV_KERNEL_ADDR 0xffd00000
  60. #define MV_INITRD_ADDR 0xff900000
  61. #define MV_INITRD_LENGTH 0x00400000
  62. #define MV_SCRATCH_ADDR 0x00000000
  63. #define MV_SCRATCH_LENGTH MV_INITRD_LENGTH
  64. #define MV_SCRIPT_ADDR 0xff840000
  65. #define MV_SCRIPT_ADDR2 0xff850000
  66. #define MV_DTB_ADDR 0xfffc0000
  67. #define CONFIG_SHOW_BOOT_PROGRESS 1
  68. #define MV_KERNEL_ADDR_RAM 0x00100000
  69. #define MV_DTB_ADDR_RAM 0x00600000
  70. #define MV_INITRD_ADDR_RAM 0x01000000
  71. /* pass open firmware flat tree */
  72. #define CONFIG_OF_LIBFDT 1
  73. #define CONFIG_OF_BOARD_SETUP 1
  74. #define OF_CPU "PowerPC,5200@0"
  75. #define OF_SOC "soc5200@f0000000"
  76. #define OF_TBCLK (bd->bi_busfreq / 4)
  77. #define MV_DTB_NAME mvbc-p.dtb
  78. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  79. /*
  80. * Supported commands
  81. */
  82. #include <config_cmd_default.h>
  83. #define CONFIG_CMD_CACHE
  84. #define CONFIG_CMD_NET
  85. #define CONFIG_CMD_PING
  86. #define CONFIG_CMD_DHCP
  87. #define CONFIG_CMD_SDRAM
  88. #define CONFIG_CMD_PCI
  89. #define CONFIG_CMD_FPGA
  90. #define CONFIG_CMD_I2C
  91. #undef CONFIG_WATCHDOG
  92. #define CONFIG_BOOTP_VENDOREX
  93. #define CONFIG_BOOTP_SUBNETMASK
  94. #define CONFIG_BOOTP_GATEWAY
  95. #define CONFIG_BOOTP_DNS
  96. #define CONFIG_BOOTP_DNS2
  97. #define CONFIG_BOOTP_HOSTNAME
  98. #define CONFIG_BOOTP_BOOTFILESIZE
  99. #define CONFIG_BOOTP_BOOTPATH
  100. #define CONFIG_BOOTP_NTPSERVER
  101. #define CONFIG_BOOTP_RANDOM_DELAY
  102. #define CONFIG_BOOTP_SEND_HOSTNAME
  103. /*
  104. * Autoboot
  105. */
  106. #define CONFIG_BOOTDELAY 2
  107. #define CONFIG_AUTOBOOT_KEYED
  108. #define CONFIG_AUTOBOOT_STOP_STR "s"
  109. #define CONFIG_ZERO_BOOTDELAY_CHECK
  110. #define CONFIG_RESET_TO_RETRY 1000
  111. #define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \
  112. then source ${script_addr}; \
  113. else source ${script_addr2}; \
  114. fi;"
  115. #define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
  116. #define CONFIG_ENV_OVERWRITE
  117. #define XMK_STR(x) #x
  118. #define MK_STR(x) XMK_STR(x)
  119. #define CONFIG_EXTRA_ENV_SETTINGS \
  120. "console_nr=0\0" \
  121. "console=yes\0" \
  122. "stdin=serial\0" \
  123. "stdout=serial\0" \
  124. "stderr=serial\0" \
  125. "fpga=0\0" \
  126. "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
  127. "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
  128. "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
  129. "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
  130. "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
  131. "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
  132. "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
  133. "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
  134. "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
  135. "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
  136. "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
  137. "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
  138. "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
  139. "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
  140. "mv_version=" U_BOOT_VERSION "\0" \
  141. "dhcp_client_id=" MK_STR(MV_CI) "\0" \
  142. "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
  143. "netretry=no\0" \
  144. "use_static_ipaddr=no\0" \
  145. "static_ipaddr=192.168.90.10\0" \
  146. "static_netmask=255.255.255.0\0" \
  147. "static_gateway=0.0.0.0\0" \
  148. "initrd_name=uInitrd.mvbc-p-rfs\0" \
  149. "zcip=no\0" \
  150. "netboot=yes\0" \
  151. "mvtest=Ff\0" \
  152. "tried_bootfromflash=no\0" \
  153. "tried_bootfromnet=no\0" \
  154. "use_dhcp=yes\0" \
  155. "gev_start=yes\0" \
  156. "mvbcdma_debug=0\0" \
  157. "mvbcia_debug=0\0" \
  158. "propdev_debug=0\0" \
  159. "gevss_debug=0\0" \
  160. "watchdog=1\0" \
  161. "sensor_cnt=1\0" \
  162. ""
  163. #undef XMK_STR
  164. #undef MK_STR
  165. /*
  166. * IPB Bus clocking configuration.
  167. */
  168. #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
  169. #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
  170. /*
  171. * Flash configuration
  172. */
  173. #undef CONFIG_FLASH_16BIT
  174. #define CONFIG_SYS_FLASH_CFI
  175. #define CONFIG_FLASH_CFI_DRIVER
  176. #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
  177. #define CONFIG_SYS_FLASH_EMPTY_INFO
  178. #define CONFIG_SYS_FLASH_ERASE_TOUT 50000
  179. #define CONFIG_SYS_FLASH_WRITE_TOUT 1000
  180. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  181. #define CONFIG_SYS_MAX_FLASH_SECT 256
  182. #define CONFIG_SYS_LOWBOOT
  183. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
  184. #define CONFIG_SYS_FLASH_SIZE 0x00800000
  185. /*
  186. * Environment settings
  187. */
  188. #define CONFIG_ENV_IS_IN_FLASH
  189. #undef CONFIG_SYS_FLASH_PROTECTION
  190. #define CONFIG_ENV_ADDR 0xFFFE0000
  191. #define CONFIG_ENV_SIZE 0x10000
  192. #define CONFIG_ENV_SECT_SIZE 0x10000
  193. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
  194. #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  195. /*
  196. * Memory map
  197. */
  198. #define CONFIG_SYS_MBAR 0xF0000000
  199. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  200. #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
  201. #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
  202. #define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
  203. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  204. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  205. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  206. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  207. #define CONFIG_SYS_RAMBOOT 1
  208. #endif
  209. /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
  210. #define CONFIG_SYS_MONITOR_LEN (512 << 10)
  211. #define CONFIG_SYS_MALLOC_LEN (512 << 10)
  212. #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
  213. /*
  214. * I2C configuration
  215. */
  216. #define CONFIG_HARD_I2C 1
  217. #define CONFIG_SYS_I2C_MODULE 1
  218. #define CONFIG_SYS_I2C_SPEED 86000
  219. #define CONFIG_SYS_I2C_SLAVE 0x7F
  220. /*
  221. * Ethernet configuration
  222. */
  223. #define CONFIG_NET_RETRY_COUNT 5
  224. #define CONFIG_E1000
  225. #define CONFIG_E1000_FALLBACK_MAC { 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
  226. #undef CONFIG_MPC5xxx_FEC
  227. #undef CONFIG_PHY_ADDR
  228. #define CONFIG_NETDEV eth0
  229. /*
  230. * Miscellaneous configurable options
  231. */
  232. #define CONFIG_SYS_HUSH_PARSER
  233. #define CONFIG_CMDLINE_EDITING
  234. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  235. #undef CONFIG_SYS_LONGHELP
  236. #define CONFIG_SYS_PROMPT "=> "
  237. #ifdef CONFIG_CMD_KGDB
  238. #define CONFIG_SYS_CBSIZE 1024
  239. #else
  240. #define CONFIG_SYS_CBSIZE 256
  241. #endif
  242. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  243. #define CONFIG_SYS_MAXARGS 16
  244. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  245. #define CONFIG_SYS_MEMTEST_START 0x00800000
  246. #define CONFIG_SYS_MEMTEST_END 0x02f00000
  247. #define CONFIG_SYS_HZ 1000
  248. /* default load address */
  249. #define CONFIG_SYS_LOAD_ADDR 0x02000000
  250. /* default location for tftp and bootm */
  251. #define CONFIG_LOADADDR 0x00200000
  252. /*
  253. * Various low-level settings
  254. */
  255. #define CONFIG_SYS_GPS_PORT_CONFIG 0x20000004
  256. #define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
  257. #define CONFIG_SYS_HID0_FINAL HID0_ICE
  258. #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
  259. #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
  260. #define CONFIG_SYS_BOOTCS_CFG 0x00047800
  261. #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
  262. #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
  263. #define CONFIG_SYS_CS_BURST 0x000000f0
  264. #define CONFIG_SYS_CS_DEADCYCLE 0x33333303
  265. #define CONFIG_SYS_RESET_ADDRESS 0x00000100
  266. #undef FPGA_DEBUG
  267. #undef CONFIG_SYS_FPGA_PROG_FEEDBACK
  268. #define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
  269. #define CONFIG_FPGA_ALTERA 1
  270. #define CONFIG_FPGA_CYCLON2 1
  271. #define CONFIG_FPGA_COUNT 1
  272. #endif