zipitz2.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214
  1. /*
  2. * Copyright (C) 2009
  3. * Marek Vasut <marek.vasut@gmail.com>
  4. *
  5. * Heavily based on pxa255_idp platform
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <common.h>
  26. #include <command.h>
  27. #include <serial.h>
  28. #include <asm/arch/hardware.h>
  29. #include <spi.h>
  30. #include <asm/io.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #ifdef CONFIG_CMD_SPI
  33. void lcd_start(void);
  34. #else
  35. inline void lcd_start(void) {};
  36. #endif
  37. /*
  38. * Miscelaneous platform dependent initialisations
  39. */
  40. int board_init (void)
  41. {
  42. /* We have RAM, disable cache */
  43. dcache_disable();
  44. icache_disable();
  45. /* arch number of Z2 */
  46. gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2;
  47. /* adress of boot parameters */
  48. gd->bd->bi_boot_params = 0xa0000100;
  49. /* Enable LCD */
  50. lcd_start();
  51. return 0;
  52. }
  53. struct serial_device *default_serial_console (void)
  54. {
  55. return &serial_stuart_device;
  56. }
  57. extern void pxa_dram_init(void);
  58. int dram_init(void)
  59. {
  60. pxa_dram_init();
  61. gd->ram_size = PHYS_SDRAM_1_SIZE;
  62. return 0;
  63. }
  64. void dram_init_banksize(void)
  65. {
  66. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  67. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  68. }
  69. #ifdef CONFIG_CMD_SPI
  70. struct {
  71. unsigned char reg;
  72. unsigned short data;
  73. unsigned char mdelay;
  74. } lcd_data[] = {
  75. { 0x07, 0x0000, 0 },
  76. { 0x13, 0x0000, 10 },
  77. { 0x11, 0x3004, 0 },
  78. { 0x14, 0x200F, 0 },
  79. { 0x10, 0x1a20, 0 },
  80. { 0x13, 0x0040, 50 },
  81. { 0x13, 0x0060, 0 },
  82. { 0x13, 0x0070, 200 },
  83. { 0x01, 0x0127, 0 },
  84. { 0x02, 0x0700, 0 },
  85. { 0x03, 0x1030, 0 },
  86. { 0x08, 0x0208, 0 },
  87. { 0x0B, 0x0620, 0 },
  88. { 0x0C, 0x0110, 0 },
  89. { 0x30, 0x0120, 0 },
  90. { 0x31, 0x0127, 0 },
  91. { 0x32, 0x0000, 0 },
  92. { 0x33, 0x0503, 0 },
  93. { 0x34, 0x0727, 0 },
  94. { 0x35, 0x0124, 0 },
  95. { 0x36, 0x0706, 0 },
  96. { 0x37, 0x0701, 0 },
  97. { 0x38, 0x0F00, 0 },
  98. { 0x39, 0x0F00, 0 },
  99. { 0x40, 0x0000, 0 },
  100. { 0x41, 0x0000, 0 },
  101. { 0x42, 0x013f, 0 },
  102. { 0x43, 0x0000, 0 },
  103. { 0x44, 0x013f, 0 },
  104. { 0x45, 0x0000, 0 },
  105. { 0x46, 0xef00, 0 },
  106. { 0x47, 0x013f, 0 },
  107. { 0x48, 0x0000, 0 },
  108. { 0x07, 0x0015, 30 },
  109. { 0x07, 0x0017, 0 },
  110. { 0x20, 0x0000, 0 },
  111. { 0x21, 0x0000, 0 },
  112. { 0x22, 0x0000, 0 },
  113. };
  114. void zipitz2_spi_sda(int set)
  115. {
  116. /* GPIO 13 */
  117. if (set)
  118. writel((1 << 13), GPSR0);
  119. else
  120. writel((1 << 13), GPCR0);
  121. }
  122. void zipitz2_spi_scl(int set)
  123. {
  124. /* GPIO 22 */
  125. if (set)
  126. writel((1 << 22), GPCR0);
  127. else
  128. writel((1 << 22), GPSR0);
  129. }
  130. unsigned char zipitz2_spi_read(void)
  131. {
  132. /* GPIO 40 */
  133. return !!(readl(GPLR1) & (1 << 8));
  134. }
  135. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  136. {
  137. /* Always valid */
  138. return 1;
  139. }
  140. void spi_cs_activate(struct spi_slave *slave)
  141. {
  142. /* GPIO 88 low */
  143. writel((1 << 24), GPCR2);
  144. }
  145. void spi_cs_deactivate(struct spi_slave *slave)
  146. {
  147. /* GPIO 88 high */
  148. writel((1 << 24), GPSR2);
  149. }
  150. void lcd_start(void)
  151. {
  152. int i;
  153. unsigned char reg[3] = { 0x74, 0x00, 0 };
  154. unsigned char data[3] = { 0x76, 0, 0 };
  155. unsigned char dummy[3] = { 0, 0, 0 };
  156. /* PWM2 AF */
  157. writel(readl(GAFR0_L) | 0x00800000, GAFR0_L);
  158. /* Enable clock to all PWM */
  159. writel(readl(CKEN) | 0x3, CKEN);
  160. /* Configure PWM2 */
  161. writel(0x4f, PWM_CTRL2);
  162. writel(0x2ff, PWM_PWDUTY2);
  163. writel(792, PWM_PERVAL2);
  164. /* Toggle the reset pin to reset the LCD */
  165. writel((1 << 19), GPSR0);
  166. udelay(100000);
  167. writel((1 << 19), GPCR0);
  168. udelay(20000);
  169. writel((1 << 19), GPSR0);
  170. udelay(20000);
  171. /* Program the LCD init sequence */
  172. for (i = 0; i < sizeof(lcd_data) / sizeof(lcd_data[0]); i++) {
  173. reg[0] = 0x74;
  174. reg[1] = 0x0;
  175. reg[2] = lcd_data[i].reg;
  176. spi_xfer(NULL, 24, reg, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
  177. data[0] = 0x76;
  178. data[1] = lcd_data[i].data >> 8;
  179. data[2] = lcd_data[i].data & 0xff;
  180. spi_xfer(NULL, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
  181. if (lcd_data[i].mdelay)
  182. udelay(lcd_data[i].mdelay * 1000);
  183. }
  184. writel((1 << 11), GPSR0);
  185. }
  186. #endif