ixp425pci.h 6.0 KB

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  1. /*
  2. * IXP PCI Init
  3. * (C) Copyright 2004 eslab.whut.edu.cn
  4. * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #ifndef _IXP425PCI_H
  25. #define _IXP425PCI_H
  26. #define OK 0
  27. #define ERROR -1
  28. struct pci_controller;
  29. extern void pci_ixp_init(struct pci_controller *hose);
  30. /* Mask definitions*/
  31. #define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f
  32. #define PCI_NP_CBE_BESL (4)
  33. #define PCI_NP_AD_FUNCSL (8)
  34. /*Register addressing definitions for PCI controller configuration
  35. and status registers*/
  36. #define PCI_CSR_BASE (0xC0000000)
  37. /*
  38. #define PCI_NP_AD_OFFSET (0x00)
  39. #define PCI_NP_CBE_OFFSET (0x04)
  40. #define PCI_NP_WDATA_OFFSET (0x08)
  41. #define PCI_NP_RDATA_OFFSET (0x0C)
  42. #define PCI_CRP_OFFSET (0x10)
  43. #define PCI_CRP_WDATA_OFFSET (0x14)
  44. #define PCI_CRP_RDATA_OFFSET (0x18)
  45. #define PCI_CSR_OFFSET (0x1C)
  46. #define PCI_ISR_OFFSET (0x20)
  47. #define PCI_INTEN_OFFSET (0x24)
  48. #define PCI_DMACTRL_OFFSET (0x28)
  49. #define PCI_AHBMEMBASE_OFFSET (0x2C)
  50. #define PCI_AHBIOBASE_OFFSET (0x30)
  51. #define PCI_PCIMEMBASE_OFFSET (0x34)
  52. #define PCI_AHBDOORBELL_OFFSET (0x38)
  53. #define PCI_PCIDOORBELL_OFFSET (0x3C)
  54. #define PCI_ATPDMA0_AHBADDR (0x40)
  55. #define PCI_ATPDMA0_PCIADDR (0x44)
  56. #define PCI_ATPDMA0_LENADDR (0x48)
  57. #define PCI_ATPDMA1_AHBADDR (0x4C)
  58. #define PCI_ATPDMA1_PCIADDR (0x50)
  59. #define PCI_ATPDMA1_LENADDR (0x54)
  60. #define PCI_PTADMA0_AHBADDR (0x58)
  61. #define PCI_PTADMA0_PCIADDR (0x5C)
  62. #define PCI_PTADMA0_LENADDR (0x60)
  63. #define PCI_PTADMA1_AHBADDR (0x64)
  64. #define PCI_PTADMA1_PCIADDR (0x68)
  65. #define PCI_PTADMA1_LENADDR (0x6C)
  66. */
  67. /*Non prefetch registers bit definitions*/
  68. /*
  69. #define NP_CMD_INTACK (0x0)
  70. #define NP_CMD_SPECIAL (0x1)
  71. #define NP_CMD_IOREAD (0x2)
  72. #define NP_CMD_IOWRITE (0x3)
  73. #define NP_CMD_MEMREAD (0x6)
  74. #define NP_CMD_MEMWRITE (0x7)
  75. #define NP_CMD_CONFIGREAD (0xa)
  76. #define NP_CMD_CONFIGWRITE (0xb)
  77. */
  78. /*Configuration Port register bit definitions*/
  79. #define PCI_CRP_WRITE BIT(16)
  80. /*ISR (Interrupt status) Register bit definitions*/
  81. #define PCI_ISR_PSE BIT(0)
  82. #define PCI_ISR_PFE BIT(1)
  83. #define PCI_ISR_PPE BIT(2)
  84. #define PCI_ISR_AHBE BIT(3)
  85. #define PCI_ISR_APDC BIT(4)
  86. #define PCI_ISR_PADC BIT(5)
  87. #define PCI_ISR_ADB BIT(6)
  88. #define PCI_ISR_PDB BIT(7)
  89. /*INTEN (Interrupt Enable) Register bit definitions*/
  90. #define PCI_INTEN_PSE BIT(0)
  91. #define PCI_INTEN_PFE BIT(1)
  92. #define PCI_INTEN_PPE BIT(2)
  93. #define PCI_INTEN_AHBE BIT(3)
  94. #define PCI_INTEN_APDC BIT(4)
  95. #define PCI_INTEN_PADC BIT(5)
  96. #define PCI_INTEN_ADB BIT(6)
  97. #define PCI_INTEN_PDB BIT(7)
  98. /*PCI configuration regs.*/
  99. #define PCI_CFG_VENDOR_ID 0x00
  100. #define PCI_CFG_DEVICE_ID 0x02
  101. #define PCI_CFG_COMMAND 0x04
  102. #define PCI_CFG_STATUS 0x06
  103. #define PCI_CFG_REVISION 0x08
  104. #define PCI_CFG_PROGRAMMING_IF 0x09
  105. #define PCI_CFG_SUBCLASS 0x0a
  106. #define PCI_CFG_CLASS 0x0b
  107. #define PCI_CFG_CACHE_LINE_SIZE 0x0c
  108. #define PCI_CFG_LATENCY_TIMER 0x0d
  109. #define PCI_CFG_HEADER_TYPE 0x0e
  110. #define PCI_CFG_BIST 0x0f
  111. #define PCI_CFG_BASE_ADDRESS_0 0x10
  112. #define PCI_CFG_BASE_ADDRESS_1 0x14
  113. #define PCI_CFG_BASE_ADDRESS_2 0x18
  114. #define PCI_CFG_BASE_ADDRESS_3 0x1c
  115. #define PCI_CFG_BASE_ADDRESS_4 0x20
  116. #define PCI_CFG_BASE_ADDRESS_5 0x24
  117. #define PCI_CFG_CIS 0x28
  118. #define PCI_CFG_SUB_VENDOR_ID 0x2c
  119. #define PCI_CFG_SUB_SYSTEM_ID 0x2e
  120. #define PCI_CFG_EXPANSION_ROM 0x30
  121. #define PCI_CFG_RESERVED_0 0x34
  122. #define PCI_CFG_RESERVED_1 0x38
  123. #define PCI_CFG_DEV_INT_LINE 0x3c
  124. #define PCI_CFG_DEV_INT_PIN 0x3d
  125. #define PCI_CFG_MIN_GRANT 0x3e
  126. #define PCI_CFG_MAX_LATENCY 0x3f
  127. #define PCI_CFG_SPECIAL_USE 0x41
  128. #define PCI_CFG_MODE 0x43
  129. #define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */
  130. #define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
  131. #define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
  132. #define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */
  133. #define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */
  134. #define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */
  135. #define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */
  136. #define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */
  137. #define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */
  138. #define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */
  139. /*CSR Register bit definitions*/
  140. #define PCI_CSR_HOST BIT(0)
  141. #define PCI_CSR_ARBEN BIT(1)
  142. #define PCI_CSR_ADS BIT(2)
  143. #define PCI_CSR_PDS BIT(3)
  144. #define PCI_CSR_ABE BIT(4)
  145. #define PCI_CSR_DBT BIT(5)
  146. #define PCI_CSR_ASE BIT(8)
  147. #define PCI_CSR_IC BIT(15)
  148. /*Configuration command bit definitions*/
  149. #define PCI_CFG_CMD_IOAE BIT(0)
  150. #define PCI_CFG_CMD_MAE BIT(1)
  151. #define PCI_CFG_CMD_BME BIT(2)
  152. #define PCI_CFG_CMD_MWIE BIT(4)
  153. #define PCI_CFG_CMD_SER BIT(8)
  154. #define PCI_CFG_CMD_FBBE BIT(9)
  155. #define PCI_CFG_CMD_MDPE BIT(24)
  156. #define PCI_CFG_CMD_STA BIT(27)
  157. #define PCI_CFG_CMD_RTA BIT(28)
  158. #define PCI_CFG_CMD_RMA BIT(29)
  159. #define PCI_CFG_CMD_SSE BIT(30)
  160. #define PCI_CFG_CMD_DPE BIT(31)
  161. /*DMACTRL DMA Control and status Register*/
  162. #define PCI_DMACTRL_APDCEN BIT(0)
  163. #define PCI_DMACTRL_APDC0 BIT(4)
  164. #define PCI_DMACTRL_APDE0 BIT(5)
  165. #define PCI_DMACTRL_APDC1 BIT(6)
  166. #define PCI_DMACTRL_APDE1 BIT(7)
  167. #define PCI_DMACTRL_PADCEN BIT(8)
  168. #define PCI_DMACTRL_PADC0 BIT(12)
  169. #define PCI_DMACTRL_PADE0 BIT(13)
  170. #define PCI_DMACTRL_PADC1 BIT(14)
  171. #define PCI_DMACTRL_PADE1 BIT(15)
  172. #endif