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uboot-vybrid_pu...
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arch
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arm
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include
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asm
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arch-am33xx
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hardware.h

hardware.h 2.2 KB
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  1. /*
    2. 

  2.  * hardware.h
    3. 

  3.  *
    4. 

  4.  * hardware specific header
    5. 

  5.  *
    6. 

  6.  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
    7. 

  7.  *
    8. 

  8.  * This program is free software; you can redistribute it and/or
    9. 

  9.  * modify it under the terms of the GNU General Public License as
    10. 

  10.  * published by the Free Software Foundation; either version 2 of
    11. 

  11.  * the License, or (at your option) any later version.
    12. 

  12.  *
    13. 

  13.  * This program is distributed in the hope that it will be useful,
    14. 

  14.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15. 

  15.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
    16. 

  16.  * GNU General Public License for more details.
    17. 

  17.  */
    18. 

  18. 

  19. #ifndef __AM33XX_HARDWARE_H
    20. 

  20. #define __AM33XX_HARDWARE_H
    21. 

  21. 

  22. /* Module base addresses */
    23. 

  23. #define LOW_LEVEL_SRAM_STACK		0x4030B7FC
    24. 

  24. #define UART0_BASE			0x44E09000
    25. 

  25. 

  26. /* DM Timer base addresses */
    27. 

  27. #define DM_TIMER0_BASE			0x4802C000
    28. 

  28. #define DM_TIMER1_BASE			0x4802E000
    29. 

  29. #define DM_TIMER2_BASE			0x48040000
    30. 

  30. #define DM_TIMER3_BASE			0x48042000
    31. 

  31. #define DM_TIMER4_BASE			0x48044000
    32. 

  32. #define DM_TIMER5_BASE			0x48046000
    33. 

  33. #define DM_TIMER6_BASE			0x48048000
    34. 

  34. #define DM_TIMER7_BASE			0x4804A000
    35. 

  35. 

  36. /* GPIO Base address */
    37. 

  37. #define GPIO0_BASE			0x48032000
    38. 

  38. #define GPIO1_BASE			0x4804C000
    39. 

  39. #define GPIO2_BASE			0x481AC000
    40. 

  40. 

  41. /* BCH Error Location Module */
    42. 

  42. #define ELM_BASE			0x48080000
    43. 

  43. 

  44. /* Watchdog Timer */
    45. 

  45. #define WDT_BASE			0x44E35000
    46. 

  46. 

  47. /* Control Module Base Address */
    48. 

  48. #define CTRL_BASE			0x44E10000
    49. 

  49. 

  50. /* PRCM Base Address */
    51. 

  51. #define PRCM_BASE			0x44E00000
    52. 

  52. 

  53. /* EMIF Base address */
    54. 

  54. #define EMIF4_0_CFG_BASE		0x4C000000
    55. 

  55. #define EMIF4_1_CFG_BASE		0x4D000000
    56. 

  56. #define DMM_BASE			0x4E000000
    57. 

  57. 

  58. /* PLL related registers */
    59. 

  59. #define CM_PER				0x44E00000
    60. 

  60. #define CM_WKUP				0x44E00400
    61. 

  61. #define CM_DPLL				0x44E00500
    62. 

  62. #define CM_DEVICE			0x44E00700
    63. 

  63. #define CM_CEFUSE			0x44E00A00
    64. 

  64. #define PRM_DEVICE			0x44E00F00
    65. 

  65. 

  66. /* VTP Base address */
    67. 

  67. #define VTP0_CTRL_ADDR			0x44E10E0C
    68. 

  68. 

  69. /* DDR Base address */
    70. 

  70. #define DDR_CTRL_ADDR			0x44E10E04
    71. 

  71. #define DDR_CONTROL_BASE_ADDR		0x44E11404
    72. 

  72. #define DDR_PHY_BASE_ADDR		0x44E12000
    73. 

  73. #define DDR_PHY_BASE_ADDR2		0x44E120A4
    74. 

  74. 

  75. /* UART */
    76. 

  76. #define DEFAULT_UART_BASE		UART0_BASE
    77. 

  77. 

  78. #define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
    79. 

  79. #define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
    80. 

  80. 

  81. #endif /* __AM33XX_HARDWARE_H */
    82.