mem.c 4.2 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Texas Instruments, <www.ti.com>
  4. *
  5. * Author :
  6. * Manikandan Pillai <mani.pillai@ti.com>
  7. *
  8. * Initial Code from:
  9. * Richard Woodruff <r-woodruff2@ti.com>
  10. * Syed Mohammed Khasim <khasim@ti.com>
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <common.h>
  28. #include <asm/io.h>
  29. #include <asm/arch/mem.h>
  30. #include <asm/arch/sys_proto.h>
  31. #include <command.h>
  32. struct gpmc *gpmc_cfg;
  33. #if defined(CONFIG_CMD_NAND)
  34. static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
  35. M_NAND_GPMC_CONFIG1,
  36. M_NAND_GPMC_CONFIG2,
  37. M_NAND_GPMC_CONFIG3,
  38. M_NAND_GPMC_CONFIG4,
  39. M_NAND_GPMC_CONFIG5,
  40. M_NAND_GPMC_CONFIG6, 0
  41. };
  42. #if defined(CONFIG_ENV_IS_IN_NAND)
  43. #define GPMC_CS 0
  44. #else
  45. #define GPMC_CS 1
  46. #endif
  47. #endif
  48. #if defined(CONFIG_CMD_ONENAND)
  49. static const u32 gpmc_onenand[GPMC_MAX_REG] = {
  50. ONENAND_GPMC_CONFIG1,
  51. ONENAND_GPMC_CONFIG2,
  52. ONENAND_GPMC_CONFIG3,
  53. ONENAND_GPMC_CONFIG4,
  54. ONENAND_GPMC_CONFIG5,
  55. ONENAND_GPMC_CONFIG6, 0
  56. };
  57. #if defined(CONFIG_ENV_IS_IN_ONENAND)
  58. #define GPMC_CS 0
  59. #else
  60. #define GPMC_CS 1
  61. #endif
  62. #endif
  63. /********************************************************
  64. * mem_ok() - test used to see if timings are correct
  65. * for a part. Helps in guessing which part
  66. * we are currently using.
  67. *******************************************************/
  68. u32 mem_ok(u32 cs)
  69. {
  70. u32 val1, val2, addr;
  71. u32 pattern = 0x12345678;
  72. addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
  73. writel(0x0, addr + 0x400); /* clear pos A */
  74. writel(pattern, addr); /* pattern to pos B */
  75. writel(0x0, addr + 4); /* remove pattern off the bus */
  76. val1 = readl(addr + 0x400); /* get pos A value */
  77. val2 = readl(addr); /* get val2 */
  78. if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */
  79. return 0;
  80. else
  81. return 1;
  82. }
  83. void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
  84. u32 size)
  85. {
  86. writel(0, &cs->config7);
  87. sdelay(1000);
  88. /* Delay for settling */
  89. writel(gpmc_config[0], &cs->config1);
  90. writel(gpmc_config[1], &cs->config2);
  91. writel(gpmc_config[2], &cs->config3);
  92. writel(gpmc_config[3], &cs->config4);
  93. writel(gpmc_config[4], &cs->config5);
  94. writel(gpmc_config[5], &cs->config6);
  95. /* Enable the config */
  96. writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
  97. (1 << 6)), &cs->config7);
  98. sdelay(2000);
  99. }
  100. /*****************************************************
  101. * gpmc_init(): init gpmc bus
  102. * Init GPMC for x16, MuxMode (SDRAM in x32).
  103. * This code can only be executed from SRAM or SDRAM.
  104. *****************************************************/
  105. void gpmc_init(void)
  106. {
  107. /* putting a blanket check on GPMC based on ZeBu for now */
  108. gpmc_cfg = (struct gpmc *)GPMC_BASE;
  109. #if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
  110. const u32 *gpmc_config = NULL;
  111. u32 base = 0;
  112. u32 size = 0;
  113. #endif
  114. u32 config = 0;
  115. /* global settings */
  116. writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */
  117. writel(0, &gpmc_cfg->timeout_control);/* timeout disable */
  118. config = readl(&gpmc_cfg->config);
  119. config &= (~0xf00);
  120. writel(config, &gpmc_cfg->config);
  121. /*
  122. * Disable the GPMC0 config set by ROM code
  123. * It conflicts with our MPDB (both at 0x08000000)
  124. */
  125. writel(0, &gpmc_cfg->cs[0].config7);
  126. sdelay(1000);
  127. #if defined(CONFIG_CMD_NAND) /* CS 0 */
  128. gpmc_config = gpmc_m_nand;
  129. base = PISMO1_NAND_BASE;
  130. size = PISMO1_NAND_SIZE;
  131. enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
  132. #endif
  133. #if defined(CONFIG_CMD_ONENAND)
  134. gpmc_config = gpmc_onenand;
  135. base = PISMO1_ONEN_BASE;
  136. size = PISMO1_ONEN_SIZE;
  137. enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
  138. #endif
  139. }