et1011c.c 1.5 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253
  1. /*
  2. * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board.
  3. *
  4. * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <common.h>
  21. #include <net.h>
  22. #include <miiphy.h>
  23. #include <asm/arch/emac_defs.h>
  24. #ifdef CONFIG_DRIVER_TI_EMAC
  25. #ifdef CONFIG_CMD_NET
  26. /* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */
  27. #define MII_PHY_CONFIG_REG 22
  28. /* PHY Config bits */
  29. #define PHY_SYS_CLK_EN (1 << 4)
  30. int et1011c_get_link_speed(int phy_addr)
  31. {
  32. u_int16_t data;
  33. if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) {
  34. davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data);
  35. /* Enable 125MHz clock sourced from PHY */
  36. davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG,
  37. data | PHY_SYS_CLK_EN);
  38. return (1);
  39. }
  40. return (0);
  41. }
  42. #endif /* CONFIG_CMD_NET */
  43. #endif /* CONFIG_DRIVER_ETHER */