lowlevel_init.S 4.3 KB

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  1. /*
  2. * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
  3. * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
  4. *
  5. * Modified for the at91rm9200dk board by
  6. * (C) Copyright 2004
  7. * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <config.h>
  28. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  29. #include <asm/arch/hardware.h>
  30. #include <asm/arch/at91_mc.h>
  31. #include <asm/arch/at91_pmc.h>
  32. #include <asm/arch/at91_pio.h>
  33. #define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */
  34. _MTEXT_BASE:
  35. #undef START_FROM_MEM
  36. #ifdef START_FROM_MEM
  37. .word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
  38. #else
  39. .word CONFIG_SYS_TEXT_BASE
  40. #endif
  41. .globl lowlevel_init
  42. lowlevel_init:
  43. ldr r1, =AT91_ASM_PMC_MOR
  44. /* Main oscillator Enable register */
  45. #ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
  46. ldr r0, =0x0000FF01 /* Enable main oscillator */
  47. #else
  48. ldr r0, =0x0000FF00 /* Disable main oscillator */
  49. #endif
  50. str r0, [r1] /*AT91C_CKGR_MOR] */
  51. /* Add loop to compensate Main Oscillator startup time */
  52. ldr r0, =0x00000010
  53. LoopOsc:
  54. subs r0, r0, #1
  55. bhi LoopOsc
  56. /* memory control configuration */
  57. /* this isn't very elegant, but what the heck */
  58. ldr r0, =SMRDATA
  59. ldr r1, _MTEXT_BASE
  60. sub r0, r0, r1
  61. ldr r2, =SMRDATAE
  62. sub r2, r2, r1
  63. pllloop:
  64. /* the address */
  65. ldr r1, [r0], #4
  66. /* the value */
  67. ldr r3, [r0], #4
  68. str r3, [r1]
  69. cmp r2, r0
  70. bne pllloop
  71. /* delay - this is all done by guess */
  72. ldr r0, =0x00010000
  73. /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
  74. lock:
  75. subs r0, r0, #1
  76. bhi lock
  77. ldr r0, =SMRDATA1
  78. ldr r1, _MTEXT_BASE
  79. sub r0, r0, r1
  80. ldr r2, =SMRDATA1E
  81. sub r2, r2, r1
  82. sdinit:
  83. /* the address */
  84. ldr r1, [r0], #4
  85. /* the value */
  86. ldr r3, [r0], #4
  87. str r3, [r1]
  88. cmp r2, r0
  89. bne sdinit
  90. /* switch from FastBus to Asynchronous clock mode */
  91. mrc p15, 0, r0, c1, c0, 0
  92. orr r0, r0, #ARM920T_CONTROL
  93. mcr p15, 0, r0, c1, c0, 0
  94. /* everything is fine now */
  95. mov pc, lr
  96. .ltorg
  97. SMRDATA:
  98. .word AT91_ASM_MC_EBI_CFG
  99. .word CONFIG_SYS_EBI_CFGR_VAL
  100. .word AT91_ASM_MC_SMC_CSR0
  101. .word CONFIG_SYS_SMC_CSR0_VAL
  102. .word AT91_ASM_PMC_PLLAR
  103. .word CONFIG_SYS_PLLAR_VAL
  104. .word AT91_ASM_PMC_PLLBR
  105. .word CONFIG_SYS_PLLBR_VAL
  106. .word AT91_ASM_PMC_MCKR
  107. .word CONFIG_SYS_MCKR_VAL
  108. SMRDATAE:
  109. /* here there's a delay */
  110. SMRDATA1:
  111. .word AT91_ASM_PIOC_ASR
  112. .word CONFIG_SYS_PIOC_ASR_VAL
  113. .word AT91_ASM_PIOC_BSR
  114. .word CONFIG_SYS_PIOC_BSR_VAL
  115. .word AT91_ASM_PIOC_PDR
  116. .word CONFIG_SYS_PIOC_PDR_VAL
  117. .word AT91_ASM_MC_EBI_CSA
  118. .word CONFIG_SYS_EBI_CSA_VAL
  119. .word AT91_ASM_MC_SDRAMC_CR
  120. .word CONFIG_SYS_SDRC_CR_VAL
  121. .word AT91_ASM_MC_SDRAMC_MR
  122. .word CONFIG_SYS_SDRC_MR_VAL
  123. .word CONFIG_SYS_SDRAM
  124. .word CONFIG_SYS_SDRAM_VAL
  125. .word AT91_ASM_MC_SDRAMC_MR
  126. .word CONFIG_SYS_SDRC_MR_VAL1
  127. .word CONFIG_SYS_SDRAM
  128. .word CONFIG_SYS_SDRAM_VAL
  129. .word CONFIG_SYS_SDRAM
  130. .word CONFIG_SYS_SDRAM_VAL
  131. .word CONFIG_SYS_SDRAM
  132. .word CONFIG_SYS_SDRAM_VAL
  133. .word CONFIG_SYS_SDRAM
  134. .word CONFIG_SYS_SDRAM_VAL
  135. .word CONFIG_SYS_SDRAM
  136. .word CONFIG_SYS_SDRAM_VAL
  137. .word CONFIG_SYS_SDRAM
  138. .word CONFIG_SYS_SDRAM_VAL
  139. .word CONFIG_SYS_SDRAM
  140. .word CONFIG_SYS_SDRAM_VAL
  141. .word CONFIG_SYS_SDRAM
  142. .word CONFIG_SYS_SDRAM_VAL
  143. .word AT91_ASM_MC_SDRAMC_MR
  144. .word CONFIG_SYS_SDRC_MR_VAL2
  145. .word CONFIG_SYS_SDRAM1
  146. .word CONFIG_SYS_SDRAM_VAL
  147. .word AT91_ASM_MC_SDRAMC_TR
  148. .word CONFIG_SYS_SDRC_TR_VAL
  149. .word CONFIG_SYS_SDRAM
  150. .word CONFIG_SYS_SDRAM_VAL
  151. .word AT91_ASM_MC_SDRAMC_MR
  152. .word CONFIG_SYS_SDRC_MR_VAL3
  153. .word CONFIG_SYS_SDRAM
  154. .word CONFIG_SYS_SDRAM_VAL
  155. SMRDATA1E:
  156. /* SMRDATA1 is 176 bytes long */
  157. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */