cpu.h 1.9 KB

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  1. /*
  2. * (C) Copyright 2011
  3. * Marvell Semiconductor <www.marvell.com>
  4. * Written-by: Lei Wen <leiwen@marvell.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  22. * MA 02110-1301 USA
  23. */
  24. #ifndef _PANTHEON_CPU_H
  25. #define _PANTHEON_CPU_H
  26. #include <asm/io.h>
  27. #include <asm/system.h>
  28. /*
  29. * Main Power Management (MPMU) Registers
  30. * Refer Register Datasheet 9.1
  31. */
  32. struct panthmpmu_registers {
  33. u8 pad0[0x0024];
  34. u32 ccgr; /*0x0024*/
  35. u8 pad1[0x0200 - 0x024 - 4];
  36. u32 wdtpcr; /*0x0200*/
  37. u8 pad2[0x1020 - 0x200 - 4];
  38. u32 aprr; /*0x1020*/
  39. u32 acgr; /*0x1024*/
  40. };
  41. /*
  42. * APB Clock Reset/Control Registers
  43. * Refer Register Datasheet 6.14
  44. */
  45. struct panthapb_registers {
  46. u32 uart0; /*0x000*/
  47. u32 uart1; /*0x004*/
  48. u32 gpio; /*0x008*/
  49. u8 pad0[0x034 - 0x08 - 4];
  50. u32 timers; /*0x034*/
  51. };
  52. /*
  53. * CPU Interface Registers
  54. * Refer Register Datasheet 4.3
  55. */
  56. struct panthcpu_registers {
  57. u32 chip_id; /* Chip Id Reg */
  58. u32 pad;
  59. u32 cpu_conf; /* CPU Conf Reg */
  60. u32 pad1;
  61. u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
  62. u32 pad2;
  63. u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
  64. u32 mcb_conf; /* MCB Conf Reg */
  65. u32 sys_boot_ctl; /* Sytem Boot Control */
  66. };
  67. /*
  68. * Functions
  69. */
  70. u32 panth_sdram_base(int);
  71. u32 panth_sdram_size(int);
  72. #endif /* _PANTHEON_CPU_H */