pdnb3.c 5.5 KB

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  1. /*
  2. * (C) Copyright 2006
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <command.h>
  25. #include <malloc.h>
  26. #include <asm/arch/ixp425.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. /* predefine these here for FPGA programming (before including fpga.c) */
  29. #define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data)
  30. #define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
  31. #define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
  32. #define OLD_VAL old_val
  33. static unsigned long old_val = 0;
  34. /*
  35. * include common fpga code (for prodrive boards)
  36. */
  37. #include "../common/fpga.c"
  38. /*
  39. * Miscelaneous platform dependent initialisations
  40. */
  41. int board_init(void)
  42. {
  43. /* arch number of PDNB3 */
  44. gd->bd->bi_arch_number = MACH_TYPE_PDNB3;
  45. /* adress of boot parameters */
  46. gd->bd->bi_boot_params = 0x00000100;
  47. GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
  48. GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
  49. GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
  50. GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
  51. /*
  52. * Setup GPIO's for FPGA programming
  53. */
  54. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
  55. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
  56. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
  57. GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
  58. GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
  59. GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
  60. GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
  61. GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
  62. /*
  63. * Setup GPIO's for interrupts
  64. */
  65. GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
  66. GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
  67. GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
  68. GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
  69. GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
  70. GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
  71. GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
  72. GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
  73. /*
  74. * Setup GPIO's for 33MHz clock output
  75. */
  76. *IXP425_GPIO_GPCLKR = 0x01FF0000;
  77. GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
  78. /*
  79. * Setup other chip select's
  80. */
  81. *IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
  82. return 0;
  83. }
  84. /*
  85. * Check Board Identity
  86. */
  87. int checkboard(void)
  88. {
  89. char *s = getenv("serial#");
  90. puts("Board: PDNB3");
  91. if (s != NULL) {
  92. puts(", serial# ");
  93. puts(s);
  94. }
  95. putc('\n');
  96. return (0);
  97. }
  98. int dram_init(void)
  99. {
  100. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  101. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  102. return (0);
  103. }
  104. int do_fpga_boot(unsigned char *fpgadata)
  105. {
  106. unsigned char *dst;
  107. int status;
  108. int index;
  109. int i;
  110. ulong len = CONFIG_SYS_MALLOC_LEN;
  111. /*
  112. * Setup GPIO's for FPGA programming
  113. */
  114. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
  115. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
  116. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
  117. /*
  118. * Save value so no readback is required upon programming
  119. */
  120. old_val = *IXP425_GPIO_GPOUTR;
  121. /*
  122. * First try to decompress fpga image (gzip compressed?)
  123. */
  124. dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
  125. if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
  126. printf("Error: Image has to be gzipp'ed!\n");
  127. return -1;
  128. }
  129. status = fpga_boot(dst, len);
  130. if (status != 0) {
  131. printf("\nFPGA: Booting failed ");
  132. switch (status) {
  133. case ERROR_FPGA_PRG_INIT_LOW:
  134. printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
  135. break;
  136. case ERROR_FPGA_PRG_INIT_HIGH:
  137. printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
  138. break;
  139. case ERROR_FPGA_PRG_DONE:
  140. printf("(Timeout: DONE not high after programming FPGA)\n ");
  141. break;
  142. }
  143. /* display infos on fpgaimage */
  144. index = 15;
  145. for (i=0; i<4; i++) {
  146. len = dst[index];
  147. printf("FPGA: %s\n", &(dst[index+1]));
  148. index += len+3;
  149. }
  150. putc ('\n');
  151. /* delayed reboot */
  152. for (i=5; i>0; i--) {
  153. printf("Rebooting in %2d seconds \r",i);
  154. for (index=0;index<1000;index++)
  155. udelay(1000);
  156. }
  157. putc('\n');
  158. do_reset(NULL, 0, 0, NULL);
  159. }
  160. puts("FPGA: ");
  161. /* display infos on fpgaimage */
  162. index = 15;
  163. for (i=0; i<4; i++) {
  164. len = dst[index];
  165. printf("%s ", &(dst[index+1]));
  166. index += len+3;
  167. }
  168. putc('\n');
  169. free(dst);
  170. /*
  171. * Reset FPGA
  172. */
  173. GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
  174. udelay(10);
  175. GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
  176. return (0);
  177. }
  178. int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  179. {
  180. ulong addr;
  181. if (argc < 2)
  182. return cmd_usage(cmdtp);
  183. addr = simple_strtoul(argv[1], NULL, 16);
  184. return do_fpga_boot((unsigned char *)addr);
  185. }
  186. U_BOOT_CMD(
  187. fpga, 2, 0, do_fpga,
  188. "boot FPGA",
  189. "address size\n - boot FPGA with gzipped image at <address>"
  190. );
  191. #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
  192. extern struct pci_controller hose;
  193. extern void pci_ixp_init(struct pci_controller * hose);
  194. void pci_init_board(void)
  195. {
  196. extern void pci_ixp_init (struct pci_controller *hose);
  197. pci_ixp_init(&hose);
  198. }
  199. #endif