BMW.h 9.4 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. *
  25. * Configuration settings for the CU824 board.
  26. *
  27. */
  28. /* ------------------------------------------------------------------------- */
  29. /*
  30. * board/config.h - configuration options, board specific
  31. */
  32. #ifndef __CONFIG_H
  33. #define __CONFIG_H
  34. /*
  35. * High Level Configuration Options
  36. * (easy to change)
  37. */
  38. #define CONFIG_MPC824X 1
  39. #define CONFIG_MPC8245 1
  40. #define CONFIG_BMW 1
  41. #define CONFIG_BCM570x 1 /* Use Broadcom BCM570x Ethernet Driver */
  42. #define CONFIG_TIGON3 1
  43. #define CONFIG_CONS_INDEX 1
  44. #define CONFIG_BAUDRATE 9600
  45. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  46. #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
  47. #define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */
  48. #define CONFIG_BOOTDELAY 5
  49. #define CFG_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */
  50. #define DOC_PASSIVE_PROBE 1
  51. #define CFG_DOC_SUPPORT_2000 1
  52. #define CFG_DOC_SUPPORT_MILLENNIUM 1
  53. #define CFG_DOC_SHORT_TIMEOUT 1
  54. #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
  55. CFG_CMD_DATE | \
  56. CFG_CMD_DOC | \
  57. CFG_CMD_ELF | \
  58. 0 )
  59. #if 0
  60. #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \
  61. CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE)
  62. #define CONFIG_PCI 1
  63. #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
  64. #endif
  65. /* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
  66. */
  67. #include <cmd_confdefs.h>
  68. /*
  69. * Miscellaneous configurable options
  70. */
  71. #define CFG_LONGHELP /* undef to save memory */
  72. #define CFG_PROMPT "=>" /* Monitor Command Prompt */
  73. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  74. /* Print Buffer Size
  75. */
  76. #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
  77. #define CFG_MAXARGS 8 /* Max number of command args */
  78. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  79. #define CFG_LOAD_ADDR 0x00100000 /* Default load address */
  80. /*-----------------------------------------------------------------------
  81. * Start addresses for the final memory configuration
  82. * (Set up by the startup code)
  83. * Please note that CFG_SDRAM_BASE _must_ start at 0
  84. */
  85. #define CFG_SDRAM_BASE 0x00000000
  86. #define CFG_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */
  87. #define CFG_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */
  88. #define CFG_FLASH_BASE CFG_MONITOR_BASE
  89. #define CFG_FLASH_BANKS { CFG_FLASH_BASE0_PRELIM , CFG_FLASH_BASE1_PRELIM }
  90. /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
  91. * reset vector is actually located at FFB00100, but the 8245
  92. * takes care of us.
  93. */
  94. #define CFG_RESET_ADDRESS 0xFFF00100
  95. #define CFG_EUMB_ADDR 0xFC000000
  96. #define CFG_MONITOR_BASE TEXT_BASE
  97. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  98. #define CFG_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */
  99. #define CFG_MEMTEST_START 0x00004000 /* memtest works on */
  100. #define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
  101. /* Maximum amount of RAM.
  102. */
  103. #define CFG_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */
  104. #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
  105. #undef CFG_RAMBOOT
  106. #else
  107. #define CFG_RAMBOOT
  108. #endif
  109. /*-----------------------------------------------------------------------
  110. * Definitions for initial stack pointer and data area
  111. */
  112. #define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
  113. #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  114. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  115. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  116. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  117. /*
  118. * Low Level Configuration Settings
  119. * (address mappings, register initial values, etc.)
  120. * You should know what you are doing if you make changes here.
  121. * For the detail description refer to the MPC8240 user's manual.
  122. */
  123. #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
  124. #define CFG_HZ 1000
  125. #define CFG_ETH_DEV_FN 0x7800
  126. #define CFG_ETH_IOBASE 0x00104000
  127. /* Bit-field values for MCCR1.
  128. */
  129. #define CFG_ROMNAL 0xf
  130. #define CFG_ROMFAL 0x1f
  131. #define CFG_DBUS_SIZE 0x3
  132. /* Bit-field values for MCCR2.
  133. */
  134. #define CFG_TSWAIT 0x5 /* Transaction Start Wait States timer */
  135. #define CFG_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
  136. /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
  137. */
  138. #define CFG_BSTOPRE 0 /* FIXME: was 192 */
  139. /* Bit-field values for MCCR3.
  140. */
  141. #define CFG_REFREC 2 /* Refresh to activate interval */
  142. /* Bit-field values for MCCR4.
  143. */
  144. #define CFG_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */
  145. #define CFG_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
  146. #define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
  147. #define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
  148. #define CFG_SDMODE_BURSTLEN 3 /* SDMODE Burst length */
  149. #define CFG_ACTORW 0xa /* FIXME was 2 */
  150. #define CFG_REGISTERD_TYPE_BUFFER 1
  151. #define CFG_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
  152. #define CFG_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
  153. /* Memory bank settings.
  154. * Only bits 20-29 are actually used from these vales to set the
  155. * start/end addresses. The upper two bits will always be 0, and the lower
  156. * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
  157. * address. Refer to the MPC8240 book.
  158. */
  159. #define CFG_BANK0_START 0x00000000
  160. #define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
  161. #define CFG_BANK0_ENABLE 1
  162. #define CFG_BANK1_START 0x3ff00000
  163. #define CFG_BANK1_END 0x3fffffff
  164. #define CFG_BANK1_ENABLE 0
  165. #define CFG_BANK2_START 0x3ff00000
  166. #define CFG_BANK2_END 0x3fffffff
  167. #define CFG_BANK2_ENABLE 0
  168. #define CFG_BANK3_START 0x3ff00000
  169. #define CFG_BANK3_END 0x3fffffff
  170. #define CFG_BANK3_ENABLE 0
  171. #define CFG_BANK4_START 0x3ff00000
  172. #define CFG_BANK4_END 0x3fffffff
  173. #define CFG_BANK4_ENABLE 0
  174. #define CFG_BANK5_START 0x3ff00000
  175. #define CFG_BANK5_END 0x3fffffff
  176. #define CFG_BANK5_ENABLE 0
  177. #define CFG_BANK6_START 0x3ff00000
  178. #define CFG_BANK6_END 0x3fffffff
  179. #define CFG_BANK6_ENABLE 0
  180. #define CFG_BANK7_START 0x3ff00000
  181. #define CFG_BANK7_END 0x3fffffff
  182. #define CFG_BANK7_ENABLE 0
  183. #define CFG_ODCR 0xff
  184. #define CONFIG_PCI 1 /* Include PCI support */
  185. #undef CONFIG_PCI_PNP
  186. /* PCI Memory space(s) */
  187. #define PCI_MEM_SPACE1_START 0x80000000
  188. #define PCI_MEM_SPACE2_START 0xfd000000
  189. /* ROM Spaces */
  190. #include "../board/bmw/bmw.h"
  191. /* BAT configuration */
  192. #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  193. #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  194. #define CFG_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
  195. #define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  196. #define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
  197. #define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  198. #define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
  199. #define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  200. #define CFG_DBAT0L CFG_IBAT0L
  201. #define CFG_DBAT0U CFG_IBAT0U
  202. #define CFG_DBAT1L CFG_IBAT1L
  203. #define CFG_DBAT1U CFG_IBAT1U
  204. #define CFG_DBAT2L CFG_IBAT2L
  205. #define CFG_DBAT2U CFG_IBAT2U
  206. #define CFG_DBAT3L CFG_IBAT3L
  207. #define CFG_DBAT3U CFG_IBAT3U
  208. /*
  209. * For booting Linux, the board info and command line data
  210. * have to be in the first 8 MB of memory, since this is
  211. * the maximum mapped by the Linux kernel during initialization.
  212. */
  213. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  214. /*
  215. * FLASH organization
  216. */
  217. #define CFG_MAX_FLASH_BANKS 0 /* Max number of flash banks */
  218. #define CFG_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
  219. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  220. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  221. /*
  222. * Warining: environment is not EMBEDDED in the U-Boot code.
  223. * It's stored in flash separately.
  224. */
  225. #define CFG_ENV_IS_IN_NVRAM 1
  226. #define CONFIG_ENV_OVERWRITE 1
  227. #define CFG_NVRAM_ACCESS_ROUTINE 1
  228. #define CFG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */
  229. #define CFG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */
  230. #define CFG_ENV_OFFSET 0 /* starting right at the beginning */
  231. /*
  232. * Cache Configuration
  233. */
  234. #define CFG_CACHELINE_SIZE 32
  235. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  236. # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  237. #endif
  238. /*
  239. * Internal Definitions
  240. *
  241. * Boot Flags
  242. */
  243. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  244. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  245. #endif /* __CONFIG_H */