r2dplus.c 2.0 KB

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  1. /*
  2. * Copyright (C) 2007,2008
  3. * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <ide.h>
  25. #include <netdev.h>
  26. #include <asm/processor.h>
  27. #include <asm/io.h>
  28. #include <asm/pci.h>
  29. int checkboard(void)
  30. {
  31. puts("BOARD: Renesas Solutions R2D Plus\n");
  32. return 0;
  33. }
  34. int board_init(void)
  35. {
  36. return 0;
  37. }
  38. int dram_init(void)
  39. {
  40. DECLARE_GLOBAL_DATA_PTR;
  41. gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
  42. gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
  43. printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
  44. return 0;
  45. }
  46. int board_late_init(void)
  47. {
  48. return 0;
  49. }
  50. #define FPGA_BASE 0xA4000000
  51. #define FPGA_CFCTL (FPGA_BASE + 0x04)
  52. #define CFCTL_EN (0x432)
  53. #define FPGA_CFPOW (FPGA_BASE + 0x06)
  54. #define CFPOW_ON (0x02)
  55. #define FPGA_CFCDINTCLR (FPGA_BASE + 0x2A)
  56. #define CFCDINTCLR_EN (0x01)
  57. void ide_set_reset(int idereset)
  58. {
  59. /* if reset = 1 IDE reset will be asserted */
  60. if (idereset) {
  61. outw(CFCTL_EN, FPGA_CFCTL); /* CF enable */
  62. outw(inw(FPGA_CFPOW)|CFPOW_ON, FPGA_CFPOW); /* Power OM */
  63. outw(CFCDINTCLR_EN, FPGA_CFCDINTCLR); /* Int clear */
  64. }
  65. }
  66. static struct pci_controller hose;
  67. void pci_init_board(void)
  68. {
  69. pci_sh7751_init(&hose);
  70. }
  71. int board_eth_init(bd_t *bis)
  72. {
  73. return pci_eth_init(bis);
  74. }