kbd.c 6.0 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /* Modified by Udi Finkelstein
  24. *
  25. * This file includes communication routines for SMC1 that can run even if
  26. * SMC2 have already been initialized.
  27. */
  28. #include <common.h>
  29. #include <watchdog.h>
  30. #include <commproc.h>
  31. #include <devices.h>
  32. #include <lcd.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #define SMC_INDEX 0
  35. #define PROFF_SMC PROFF_SMC1
  36. #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
  37. #define RBC823_KBD_BAUDRATE 38400
  38. #define CPM_KEYBOARD_BASE 0x1000
  39. /*
  40. * Minimal serial functions needed to use one of the SMC ports
  41. * as serial console interface.
  42. */
  43. void smc1_setbrg (void)
  44. {
  45. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  46. volatile cpm8xx_t *cp = &(im->im_cpm);
  47. /* Set up the baud rate generator.
  48. * See 8xx_io/commproc.c for details.
  49. *
  50. * Wire BRG2 to SMC1, BRG1 to SMC2
  51. */
  52. cp->cp_simode = 0x00001000;
  53. cp->cp_brgc2 =
  54. (((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN;
  55. }
  56. int smc1_init (void)
  57. {
  58. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  59. volatile smc_t *sp;
  60. volatile smc_uart_t *up;
  61. volatile cbd_t *tbdf, *rbdf;
  62. volatile cpm8xx_t *cp = &(im->im_cpm);
  63. uint dpaddr;
  64. /* initialize pointers to SMC */
  65. sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
  66. up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
  67. /* Disable transmitter/receiver.
  68. */
  69. sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
  70. /* Enable SDMA.
  71. */
  72. im->im_siu_conf.sc_sdcr = 1;
  73. /* clear error conditions */
  74. #ifdef CONFIG_SYS_SDSR
  75. im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
  76. #else
  77. im->im_sdma.sdma_sdsr = 0x83;
  78. #endif
  79. /* clear SDMA interrupt mask */
  80. #ifdef CONFIG_SYS_SDMR
  81. im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
  82. #else
  83. im->im_sdma.sdma_sdmr = 0x00;
  84. #endif
  85. /* Use Port B for SMC1 instead of other functions.
  86. */
  87. cp->cp_pbpar |= 0x000000c0;
  88. cp->cp_pbdir &= ~0x000000c0;
  89. cp->cp_pbodr &= ~0x000000c0;
  90. /* Set the physical address of the host memory buffers in
  91. * the buffer descriptors.
  92. */
  93. #ifdef CONFIG_SYS_ALLOC_DPRAM
  94. dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
  95. #else
  96. dpaddr = CPM_KEYBOARD_BASE ;
  97. #endif
  98. /* Allocate space for two buffer descriptors in the DP ram.
  99. * For now, this address seems OK, but it may have to
  100. * change with newer versions of the firmware.
  101. * damm: allocating space after the two buffers for rx/tx data
  102. */
  103. rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
  104. rbdf->cbd_bufaddr = (uint) (rbdf+2);
  105. rbdf->cbd_sc = 0;
  106. tbdf = rbdf + 1;
  107. tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
  108. tbdf->cbd_sc = 0;
  109. /* Set up the uart parameters in the parameter ram.
  110. */
  111. up->smc_rbase = dpaddr;
  112. up->smc_tbase = dpaddr+sizeof(cbd_t);
  113. up->smc_rfcr = SMC_EB;
  114. up->smc_tfcr = SMC_EB;
  115. /* Set UART mode, 8 bit, no parity, one stop.
  116. * Enable receive and transmit.
  117. */
  118. sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
  119. /* Mask all interrupts and remove anything pending.
  120. */
  121. sp->smc_smcm = 0;
  122. sp->smc_smce = 0xff;
  123. /* Set up the baud rate generator.
  124. */
  125. smc1_setbrg ();
  126. /* Make the first buffer the only buffer.
  127. */
  128. tbdf->cbd_sc |= BD_SC_WRAP;
  129. rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
  130. /* Single character receive.
  131. */
  132. up->smc_mrblr = 1;
  133. up->smc_maxidl = 0;
  134. /* Initialize Tx/Rx parameters.
  135. */
  136. while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
  137. ;
  138. cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
  139. while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
  140. ;
  141. /* Enable transmitter/receiver.
  142. */
  143. sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
  144. return (0);
  145. }
  146. void smc1_putc(const char c)
  147. {
  148. volatile cbd_t *tbdf;
  149. volatile char *buf;
  150. volatile smc_uart_t *up;
  151. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  152. volatile cpm8xx_t *cpmp = &(im->im_cpm);
  153. up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
  154. tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
  155. /* Wait for last character to go.
  156. */
  157. buf = (char *)tbdf->cbd_bufaddr;
  158. *buf = c;
  159. tbdf->cbd_datlen = 1;
  160. tbdf->cbd_sc |= BD_SC_READY;
  161. __asm__("eieio");
  162. while (tbdf->cbd_sc & BD_SC_READY) {
  163. WATCHDOG_RESET ();
  164. __asm__("eieio");
  165. }
  166. }
  167. int smc1_getc(void)
  168. {
  169. volatile cbd_t *rbdf;
  170. volatile unsigned char *buf;
  171. volatile smc_uart_t *up;
  172. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  173. volatile cpm8xx_t *cpmp = &(im->im_cpm);
  174. unsigned char c;
  175. up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
  176. rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
  177. /* Wait for character to show up.
  178. */
  179. buf = (unsigned char *)rbdf->cbd_bufaddr;
  180. while (rbdf->cbd_sc & BD_SC_EMPTY)
  181. WATCHDOG_RESET ();
  182. c = *buf;
  183. rbdf->cbd_sc |= BD_SC_EMPTY;
  184. return(c);
  185. }
  186. int smc1_tstc(void)
  187. {
  188. volatile cbd_t *rbdf;
  189. volatile smc_uart_t *up;
  190. volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  191. volatile cpm8xx_t *cpmp = &(im->im_cpm);
  192. up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
  193. rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
  194. return(!(rbdf->cbd_sc & BD_SC_EMPTY));
  195. }
  196. /* search for keyboard and register it if found */
  197. int drv_keyboard_init(void)
  198. {
  199. int error = 0;
  200. device_t kbd_dev;
  201. if (0) {
  202. /* register the keyboard */
  203. memset (&kbd_dev, 0, sizeof(device_t));
  204. strcpy(kbd_dev.name, "kbd");
  205. kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
  206. kbd_dev.putc = NULL;
  207. kbd_dev.puts = NULL;
  208. kbd_dev.getc = smc1_getc;
  209. kbd_dev.tstc = smc1_tstc;
  210. error = device_register (&kbd_dev);
  211. } else {
  212. lcd_is_enabled = 0;
  213. lcd_disable();
  214. }
  215. return error;
  216. }