lowlevel_init.S 2.0 KB

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  1. /*
  2. * Memory Setup stuff - taken from ???
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <config.h>
  23. #include <version.h>
  24. /* some parameters for the board */
  25. SYSCON2: .long 0x80001100
  26. MEMCFG1: .long 0x80000180
  27. MEMCFG2: .long 0x800001C0
  28. DRFPR: .long 0x80000200
  29. syscon2_mask: .long 0x00000004
  30. memcfg1_val: .long 0x160c1414
  31. memcfg2_mask: .long 0x0000ffff @ only set lower 16 bits
  32. memcfg2_val: .long 0x00000000 @ upper 16 bits are reserved for CS7 + CS6
  33. drfpr_val: .long 0x00000081
  34. /* setting up the memory */
  35. .globl lowlevel_init
  36. lowlevel_init:
  37. /*
  38. * DRFPR
  39. * 64kHz DRAM refresh
  40. */
  41. ldr r0, DRFPR
  42. ldr r1, drfpr_val
  43. str r1, [r0]
  44. /*
  45. * SYSCON2: clear bit 2, DRAM is 32 bits wide
  46. */
  47. ldr r0, SYSCON2
  48. ldr r2, [r0]
  49. ldr r1, syscon2_mask
  50. bic r2, r2, r1
  51. str r2, [r0]
  52. /*
  53. * MEMCFG1
  54. * Setting up Keyboard at CS3, 8 Bit, 3 Waitstates
  55. * Setting up CS8900 (Ethernet) at CS2, 32 Bit, 5 Waitstates
  56. * Setting up flash at CS0 and CS1, 32 Bit, 3 Waitstates
  57. */
  58. ldr r0, MEMCFG1
  59. ldr r1, memcfg1_val
  60. str r1, [r0]
  61. /*
  62. * MEMCFG2
  63. * Setting up ? with 0
  64. *
  65. */
  66. ldr r0, MEMCFG2
  67. ldr r2, [r0]
  68. ldr r1, memcfg2_mask
  69. bic r2, r2, r1
  70. ldr r1, memcfg2_val
  71. orr r2, r2, r1
  72. str r2, [r0]
  73. /* everything is fine now */
  74. mov pc, lr