m5253demo.c 3.6 KB

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  1. /*
  2. * (C) Copyright 2000-2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6. * Hayden Fraser (Hayden.Fraser@freescale.com)
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #include <common.h>
  27. #include <asm/immap.h>
  28. int checkboard(void)
  29. {
  30. puts("Board: ");
  31. puts("Freescale MCF5253 DEMO\n");
  32. return 0;
  33. };
  34. phys_size_t initdram(int board_type)
  35. {
  36. u32 dramsize = 0;
  37. /*
  38. * Check to see if the SDRAM has already been initialized
  39. * by a run control tool
  40. */
  41. if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
  42. u32 RC, temp;
  43. RC = (CONFIG_SYS_CLK / 1000000) >> 1;
  44. RC = (RC * 15) >> 4;
  45. /* Initialize DRAM Control Register: DCR */
  46. mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
  47. __asm__("nop");
  48. mbar_writeLong(MCFSIM_DACR0, 0x00003224);
  49. __asm__("nop");
  50. /* Initialize DMR0 */
  51. dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
  52. temp = (dramsize - 1) & 0xFFFC0000;
  53. mbar_writeLong(MCFSIM_DMR0, temp | 1);
  54. __asm__("nop");
  55. mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
  56. __asm__("nop");
  57. /* Write to this block to initiate precharge */
  58. *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
  59. __asm__("nop");
  60. /* Set RE bit in DACR */
  61. mbar_writeLong(MCFSIM_DACR0,
  62. mbar_readLong(MCFSIM_DACR0) | 0x8000);
  63. __asm__("nop");
  64. /* Wait for at least 8 auto refresh cycles to occur */
  65. udelay(500);
  66. /* Finish the configuration by issuing the MRS */
  67. mbar_writeLong(MCFSIM_DACR0,
  68. mbar_readLong(MCFSIM_DACR0) | 0x0040);
  69. __asm__("nop");
  70. *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
  71. }
  72. return dramsize;
  73. }
  74. int testdram(void)
  75. {
  76. /* TODO: XXX XXX XXX */
  77. printf("DRAM test not implemented!\n");
  78. return (0);
  79. }
  80. #ifdef CONFIG_CMD_IDE
  81. #include <ata.h>
  82. int ide_preinit(void)
  83. {
  84. return (0);
  85. }
  86. void ide_set_reset(int idereset)
  87. {
  88. volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
  89. long period;
  90. /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
  91. int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
  92. {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
  93. {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
  94. {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
  95. {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
  96. };
  97. if (idereset) {
  98. ata->cr = 0; /* control reset */
  99. udelay(100);
  100. } else {
  101. mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
  102. #define CALC_TIMING(t) (t + period - 1) / period
  103. period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
  104. /*ata->ton = CALC_TIMING (180); */
  105. ata->t1 = CALC_TIMING(piotms[2][0]);
  106. ata->t2w = CALC_TIMING(piotms[2][1]);
  107. ata->t2r = CALC_TIMING(piotms[2][1]);
  108. ata->ta = CALC_TIMING(piotms[2][8]);
  109. ata->trd = CALC_TIMING(piotms[2][7]);
  110. ata->t4 = CALC_TIMING(piotms[2][3]);
  111. ata->t9 = CALC_TIMING(piotms[2][6]);
  112. ata->cr = 0x40; /* IORDY enable */
  113. udelay(2000);
  114. ata->cr |= 0x01; /* IORDY enable */
  115. }
  116. }
  117. #endif /* CONFIG_CMD_IDE */