Strona główna Odkrywaj Pomoc
Zarejestruj się Zaloguj się
phyus
/
uboot-vybrid_public
8
0
Forkuj 0
Pliki Problemy 0 Oczekujące zmiany 0 Wiki
Drzewo: 84f7411cb9
Gałęzie Tagi
uboot-vybrid_pu...
/
board
/
ep8248
/
ep8248.c

ep8248.c 13 KB
Historia Czysty

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263 
  1. /*
    2. 

  2.  * Copyright (C) 2004 Arabella Software Ltd.
    3. 

  3.  * Yuli Barcohen <yuli@arabellasw.com>
    4. 

  4.  *
    5. 

  5.  * Support for Embedded Planet EP8248 boards.
    6. 

  6.  * Tested on EP8248E.
    7. 

  7.  *
    8. 

  8.  * See file CREDITS for list of people who contributed to this
    9. 

  9.  * project.
    10. 

  10.  *
    11. 

  11.  * This program is free software; you can redistribute it and/or
    12. 

  12.  * modify it under the terms of the GNU General Public License as
    13. 

  13.  * published by the Free Software Foundation; either version 2 of
    14. 

  14.  * the License, or (at your option) any later version.
    15. 

  15.  *
    16. 

  16.  * This program is distributed in the hope that it will be useful,
    17. 

  17.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    18. 

  18.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    19. 

  19.  * GNU General Public License for more details.
    20. 

  20.  *
    21. 

  21.  * You should have received a copy of the GNU General Public License
    22. 

  22.  * along with this program; if not, write to the Free Software
    23. 

  23.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
    24. 

  24.  * MA 02111-1307 USA
    25. 

  25.  */
    26. 

  26. 

  27. #include <common.h>
    28. 

  28. #include <mpc8260.h>
    29. 

  29. #include <ioports.h>
    30. 

  30. 

  31. /*
    32. 

  32.  * I/O Port configuration table
    33. 

  33.  *
    34. 

  34.  * if conf is 1, then that port pin will be configured at boot time
    35. 

  35.  * according to the five values podr/pdir/ppar/psor/pdat for that entry
    36. 

  36.  */
    37. 

  37. 

  38. #define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
    39. 

  39. #define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
    40. 

  40. 

  41. const iop_conf_t iop_conf_tab[4][32] = {
    42. 

  42. 

  43.     /* Port A */
    44. 

  44.     {	/*	      conf      ppar psor pdir podr pdat */
    45. 

  45. 	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
    46. 

  46. 	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
    47. 

  47. 	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
    48. 

  48. 	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
    49. 

  49. 	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
    50. 

  50. 	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
    51. 

  51. 	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
    52. 

  52. 	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
    53. 

  53. 	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
    54. 

  54. 	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22            */
    55. 

  55. 	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
    56. 

  56. 	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
    57. 

  57. 	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
    58. 

  58. 	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
    59. 

  59. 	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
    60. 

  60. 	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
    61. 

  61. 	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
    62. 

  62. 	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
    63. 

  63. 	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
    64. 

  64. 	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
    65. 

  65. 	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
    66. 

  66. 	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10            */
    67. 

  67. 	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 TxD        */
    68. 

  68. 	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 RxD        */
    69. 

  69. 	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7             */
    70. 

  70. 	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6             */
    71. 

  71. 	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5             */
    72. 

  72. 	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4             */
    73. 

  73. 	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3             */
    74. 

  74. 	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2             */
    75. 

  75. 	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1             */
    76. 

  76. 	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0             */
    77. 

  77.     },
    78. 

  78. 

  79.     /* Port B */
    80. 

  80.     {   /*	      conf      ppar psor pdir podr pdat */
    81. 

  81. 	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
    82. 

  82. 	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
    83. 

  83. 	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
    84. 

  84. 	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
    85. 

  85. 	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
    86. 

  86. 	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
    87. 

  87. 	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
    88. 

  88. 	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
    89. 

  89. 	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
    90. 

  90. 	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
    91. 

  91. 	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
    92. 

  92. 	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
    93. 

  93. 	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
    94. 

  94. 	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
    95. 

  95. 	/* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    96. 

  96. 	/* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    97. 

  97. 	/* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    98. 

  98. 	/* PB14 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    99. 

  99. 	/* PB13 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    100. 

  100. 	/* PB12 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    101. 

  101. 	/* PB11 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    102. 

  102. 	/* PB10 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    103. 

  103. 	/* PB9  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    104. 

  104. 	/* PB8  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    105. 

  105. 	/* PB7  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    106. 

  106. 	/* PB6  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    107. 

  107. 	/* PB5  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    108. 

  108. 	/* PB4  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    109. 

  109. 	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    110. 

  110. 	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    111. 

  111. 	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    112. 

  112. 	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
    113. 

  113.     },
    114. 

  114. 

  115.     /* Port C */
    116. 

  116.     {   /*	      conf      ppar psor pdir podr pdat */
    117. 

  117. 	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31            */
    118. 

  118. 	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30            */
    119. 

  119. 	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29            */
    120. 

  120. 	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28            */
    121. 

  121. 	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27            */
    122. 

  122. 	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26            */
    123. 

  123. 	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
    124. 

  124. 	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
    125. 

  125. 	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
    126. 

  126. 	/* PC22 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK10) */
    127. 

  127. 	/* PC21 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK11) */
    128. 

  128. 	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
    129. 

  129. 	/* PC19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK13) */
    130. 

  130. 	/* PC18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
    131. 

  131. 	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17            */
    132. 

  132. 	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
    133. 

  133. 	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
    134. 

  134. 	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
    135. 

  135. 	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13            */
    136. 

  136. 	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12            */
    137. 

  137. 	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11            */
    138. 

  138. 	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10            */
    139. 

  139. 	/* PC9  */ { 1,          0,   0,   1,   0,   1 }, /* MDIO            */
    140. 

  140. 	/* PC8  */ { 1,          0,   0,   1,   0,   1 }, /* MDC             */
    141. 

  141. 	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7             */
    142. 

  142. 	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6             */
    143. 

  143. 	/* PC5  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 TxD        */
    144. 

  144. 	/* PC4  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 RxD        */
    145. 

  145. 	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3             */
    146. 

  146. 	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2             */
    147. 

  147. 	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1             */
    148. 

  148. 	/* PC0  */ { 0,          0,   0,   0,   0,   0 }, /* PC0             */
    149. 

  149.     },
    150. 

  150. 

  151.     /* Port D */
    152. 

  152.     {   /*	      conf      ppar psor pdir podr pdat */
    153. 

  153. 	/* PD31 */ { 1,          1,   0,   0,   0,   0 }, /* SCC1 RxD        */
    154. 

  154. 	/* PD30 */ { 1,          1,   1,   1,   0,   0 }, /* SCC1 TxD        */
    155. 

  155. 	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29            */
    156. 

  156. 	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28            */
    157. 

  157. 	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27            */
    158. 

  158. 	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26            */
    159. 

  159. 	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25            */
    160. 

  160. 	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24            */
    161. 

  161. 	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23            */
    162. 

  162. 	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22            */
    163. 

  163. 	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21            */
    164. 

  164. 	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20            */
    165. 

  165. 	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19            */
    166. 

  166. 	/* PD18 */ { 0,          0,   0,   0,   0,   0 }, /* PD18            */
    167. 

  167. 	/* PD17 */ { 0,          0,   0,   0,   0,   0 }, /* PD17            */
    168. 

  168. 	/* PD16 */ { 0,          0,   0,   0,   0,   0 }, /* PD16            */
    169. 

  169. 	/* PD15 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SDA         */
    170. 

  170. 	/* PD14 */ { 1,          1,   1,   0,   1,   0 }, /* I2C SCL         */
    171. 

  171. 	/* PD13 */ { 0,          0,   0,   0,   0,   0 }, /* PD13            */
    172. 

  172. 	/* PD12 */ { 0,          0,   0,   0,   0,   0 }, /* PD12            */
    173. 

  173. 	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11            */
    174. 

  174. 	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10            */
    175. 

  175. 	/* PD9  */ { 0,          0,   0,   0,   0,   0 }, /* PD9             */
    176. 

  176. 	/* PD8  */ { 0,          0,   0,   0,   0,   0 }, /* PD8             */
    177. 

  177. 	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7             */
    178. 

  178. 	/* PD6  */ { 0,          0,   0,   0,   0,   0 }, /* PD6             */
    179. 

  179. 	/* PD5  */ { 0,          0,   0,   0,   0,   0 }, /* PD5             */
    180. 

  180. 	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4             */
    181. 

  181. 	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    182. 

  182. 	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    183. 

  183. 	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
    184. 

  184. 	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* non-existent    */
    185. 

  185.     }
    186. 

  186. };
    187. 

  187. 

  188. int board_early_init_f (void)
    189. 

  189. {
    190. 

  190. 	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
    191. 

  191. 

  192. 	bcsr[4] |= 0x30; /* Turn the LEDs off */
    193. 

  193. 

  194. #if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
    195. 

  195. 	bcsr[6] |= 0x10;
    196. 

  196. #endif
    197. 

  197. #if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
    198. 

  198. 	bcsr[7] |= 0x10;
    199. 

  199. #endif
    200. 

  200. 

  201. #if CONFIG_SYS_FCC1
    202. 

  202. 	bcsr[8] |= 0xC0;
    203. 

  203. #endif /* CONFIG_SYS_FCC1 */
    204. 

  204. #if CONFIG_SYS_FCC2
    205. 

  205. 	bcsr[8] |= 0x30;
    206. 

  206. #endif /* CONFIG_SYS_FCC2 */
    207. 

  207. 

  208. 	return 0;
    209. 

  209. }
    210. 

  210. 

  211. phys_size_t initdram(int board_type)
    212. 

  212. {
    213. 

  213. 	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
    214. 

  214. 	long int msize = 16L << (bcsr[2] & 3);
    215. 

  215. 

  216. #ifndef CONFIG_SYS_RAMBOOT
    217. 

  217. 	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
    218. 

  218. 	volatile memctl8260_t *memctl = &immap->im_memctl;
    219. 

  219. 	vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
    220. 

  220. 	uchar c = 0xFF;
    221. 

  221. 	uint psdmr = CONFIG_SYS_PSDMR;
    222. 

  222. 	int i;
    223. 

  223. 

  224. 	immap->im_siu_conf.sc_ppc_acr  = 0x02;
    225. 

  225. 	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
    226. 

  226. 	immap->im_siu_conf.sc_tescr1   = 0x00004000;
    227. 

  227. 

  228. 	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
    229. 

  229. 

  230. 	/* Initialise 60x bus SDRAM */
    231. 

  231. 	memctl->memc_psrt = CONFIG_SYS_PSRT;
    232. 

  232. 	memctl->memc_or1  = CONFIG_SYS_SDRAM_OR;
    233. 

  233. 	memctl->memc_br1  = CONFIG_SYS_SDRAM_BR;
    234. 

  234. 	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
    235. 

  235. 	*ramaddr = c;
    236. 

  236. 	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
    237. 

  237. 	for (i = 0; i < 8; i++)
    238. 

  238. 		*ramaddr = c;
    239. 

  239. 	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
    240. 

  240. 	*ramaddr = c;
    241. 

  241. 	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
    242. 

  242. 	*ramaddr = c;
    243. 

  243. #endif /* !CONFIG_SYS_RAMBOOT */
    244. 

  244. 

  245. 	/* Return total 60x bus SDRAM size */
    246. 

  246. 	return msize * 1024 * 1024;
    247. 

  247. }
    248. 

  248. 

  249. int checkboard(void)
    250. 

  250. {
    251. 

  251. 	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
    252. 

  252. 

  253. 	puts("Board: ");
    254. 

  254. 	switch (bcsr[0]) {
    255. 

  255. 	case 0x0C:
    256. 

  256. 		printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]);
    257. 

  257. 		break;
    258. 

  258. 	default:
    259. 

  259. 		printf("unknown: ID=%02X\n", bcsr[0]);
    260. 

  260. 	}
    261. 

  261. 

  262. 	return 0;
    263. 

  263. }
    264.