mux_omap5.h 9.5 KB

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  1. /*
  2. * (C) Copyright 2004-2009
  3. * Texas Instruments Incorporated
  4. * Richard Woodruff <r-woodruff2@ti.com>
  5. * Aneesh V <aneesh@ti.com>
  6. * Balaji Krishnamoorthy <balajitk@ti.com>
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #ifndef _MUX_OMAP5_H_
  27. #define _MUX_OMAP5_H_
  28. #include <asm/types.h>
  29. struct pad_conf_entry {
  30. u16 offset;
  31. u16 val;
  32. } __attribute__ ((__packed__));
  33. #ifdef CONFIG_OFF_PADCONF
  34. #define OFF_PD (1 << 12)
  35. #define OFF_PU (3 << 12)
  36. #define OFF_OUT_PTD (0 << 10)
  37. #define OFF_OUT_PTU (2 << 10)
  38. #define OFF_IN (1 << 10)
  39. #define OFF_OUT (0 << 10)
  40. #define OFF_EN (1 << 9)
  41. #else
  42. #define OFF_PD (0 << 12)
  43. #define OFF_PU (0 << 12)
  44. #define OFF_OUT_PTD (0 << 10)
  45. #define OFF_OUT_PTU (0 << 10)
  46. #define OFF_IN (0 << 10)
  47. #define OFF_OUT (0 << 10)
  48. #define OFF_EN (0 << 9)
  49. #endif
  50. #define IEN (1 << 8)
  51. #define IDIS (0 << 8)
  52. #define PTU (3 << 3)
  53. #define PTD (1 << 3)
  54. #define EN (1 << 3)
  55. #define DIS (0 << 3)
  56. #define M0 0
  57. #define M1 1
  58. #define M2 2
  59. #define M3 3
  60. #define M4 4
  61. #define M5 5
  62. #define M6 6
  63. #define M7 7
  64. #define SAFE_MODE M7
  65. #ifdef CONFIG_OFF_PADCONF
  66. #define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN)
  67. #define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN)
  68. #define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN)
  69. #define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN)
  70. #else
  71. #define OFF_IN_PD 0
  72. #define OFF_IN_PU 0
  73. #define OFF_OUT_PD 0
  74. #define OFF_OUT_PU 0
  75. #endif
  76. #define CORE_REVISION 0x0000
  77. #define CORE_HWINFO 0x0004
  78. #define CORE_SYSCONFIG 0x0010
  79. #define EMMC_CLK 0x0040
  80. #define EMMC_CMD 0x0042
  81. #define EMMC_DATA0 0x0044
  82. #define EMMC_DATA1 0x0046
  83. #define EMMC_DATA2 0x0048
  84. #define EMMC_DATA3 0x004a
  85. #define EMMC_DATA4 0x004c
  86. #define EMMC_DATA5 0x004e
  87. #define EMMC_DATA6 0x0050
  88. #define EMMC_DATA7 0x0052
  89. #define C2C_CLKOUT0 0x0054
  90. #define C2C_CLKOUT1 0x0056
  91. #define C2C_CLKIN0 0x0058
  92. #define C2C_CLKIN1 0x005a
  93. #define C2C_DATAIN0 0x005c
  94. #define C2C_DATAIN1 0x005e
  95. #define C2C_DATAIN2 0x0060
  96. #define C2C_DATAIN3 0x0062
  97. #define C2C_DATAIN4 0x0064
  98. #define C2C_DATAIN5 0x0066
  99. #define C2C_DATAIN6 0x0068
  100. #define C2C_DATAIN7 0x006a
  101. #define C2C_DATAOUT0 0x006c
  102. #define C2C_DATAOUT1 0x006e
  103. #define C2C_DATAOUT2 0x0070
  104. #define C2C_DATAOUT3 0x0072
  105. #define C2C_DATAOUT4 0x0074
  106. #define C2C_DATAOUT5 0x0076
  107. #define C2C_DATAOUT6 0x0078
  108. #define C2C_DATAOUT7 0x007a
  109. #define C2C_DATA8 0x007c
  110. #define C2C_DATA9 0x007e
  111. #define C2C_DATA10 0x0080
  112. #define C2C_DATA11 0x0082
  113. #define C2C_DATA12 0x0084
  114. #define C2C_DATA13 0x0086
  115. #define C2C_DATA14 0x0088
  116. #define C2C_DATA15 0x008a
  117. #define LLIA_WAKEREQOUT 0x008c
  118. #define LLIB_WAKEREQOUT 0x008e
  119. #define HSI1_ACREADY 0x0090
  120. #define HSI1_CAREADY 0x0092
  121. #define HSI1_ACWAKE 0x0094
  122. #define HSI1_CAWAKE 0x0096
  123. #define HSI1_ACFLAG 0x0098
  124. #define HSI1_ACDATA 0x009a
  125. #define HSI1_CAFLAG 0x009c
  126. #define HSI1_CADATA 0x009e
  127. #define UART1_TX 0x00a0
  128. #define UART1_CTS 0x00a2
  129. #define UART1_RX 0x00a4
  130. #define UART1_RTS 0x00a6
  131. #define HSI2_CAREADY 0x00a8
  132. #define HSI2_ACREADY 0x00aa
  133. #define HSI2_CAWAKE 0x00ac
  134. #define HSI2_ACWAKE 0x00ae
  135. #define HSI2_CAFLAG 0x00b0
  136. #define HSI2_CADATA 0x00b2
  137. #define HSI2_ACFLAG 0x00b4
  138. #define HSI2_ACDATA 0x00b6
  139. #define UART2_RTS 0x00b8
  140. #define UART2_CTS 0x00ba
  141. #define UART2_RX 0x00bc
  142. #define UART2_TX 0x00be
  143. #define USBB1_HSIC_STROBE 0x00c0
  144. #define USBB1_HSIC_DATA 0x00c2
  145. #define USBB2_HSIC_STROBE 0x00c4
  146. #define USBB2_HSIC_DATA 0x00c6
  147. #define TIMER10_PWM_EVT 0x00c8
  148. #define DSIPORTA_TE0 0x00ca
  149. #define DSIPORTA_LANE0X 0x00cc
  150. #define DSIPORTA_LANE0Y 0x00ce
  151. #define DSIPORTA_LANE1X 0x00d0
  152. #define DSIPORTA_LANE1Y 0x00d2
  153. #define DSIPORTA_LANE2X 0x00d4
  154. #define DSIPORTA_LANE2Y 0x00d6
  155. #define DSIPORTA_LANE3X 0x00d8
  156. #define DSIPORTA_LANE3Y 0x00da
  157. #define DSIPORTA_LANE4X 0x00dc
  158. #define DSIPORTA_LANE4Y 0x00de
  159. #define DSIPORTC_LANE0X 0x00e0
  160. #define DSIPORTC_LANE0Y 0x00e2
  161. #define DSIPORTC_LANE1X 0x00e4
  162. #define DSIPORTC_LANE1Y 0x00e6
  163. #define DSIPORTC_LANE2X 0x00e8
  164. #define DSIPORTC_LANE2Y 0x00ea
  165. #define DSIPORTC_LANE3X 0x00ec
  166. #define DSIPORTC_LANE3Y 0x00ee
  167. #define DSIPORTC_LANE4X 0x00f0
  168. #define DSIPORTC_LANE4Y 0x00f2
  169. #define DSIPORTC_TE0 0x00f4
  170. #define TIMER9_PWM_EVT 0x00f6
  171. #define I2C4_SCL 0x00f8
  172. #define I2C4_SDA 0x00fa
  173. #define MCSPI2_CLK 0x00fc
  174. #define MCSPI2_SIMO 0x00fe
  175. #define MCSPI2_SOMI 0x0100
  176. #define MCSPI2_CS0 0x0102
  177. #define RFBI_DATA15 0x0104
  178. #define RFBI_DATA14 0x0106
  179. #define RFBI_DATA13 0x0108
  180. #define RFBI_DATA12 0x010a
  181. #define RFBI_DATA11 0x010c
  182. #define RFBI_DATA10 0x010e
  183. #define RFBI_DATA9 0x0110
  184. #define RFBI_DATA8 0x0112
  185. #define RFBI_DATA7 0x0114
  186. #define RFBI_DATA6 0x0116
  187. #define RFBI_DATA5 0x0118
  188. #define RFBI_DATA4 0x011a
  189. #define RFBI_DATA3 0x011c
  190. #define RFBI_DATA2 0x011e
  191. #define RFBI_DATA1 0x0120
  192. #define RFBI_DATA0 0x0122
  193. #define RFBI_WE 0x0124
  194. #define RFBI_CS0 0x0126
  195. #define RFBI_A0 0x0128
  196. #define RFBI_RE 0x012a
  197. #define RFBI_HSYNC0 0x012c
  198. #define RFBI_TE_VSYNC0 0x012e
  199. #define GPIO6_182 0x0130
  200. #define GPIO6_183 0x0132
  201. #define GPIO6_184 0x0134
  202. #define GPIO6_185 0x0136
  203. #define GPIO6_186 0x0138
  204. #define GPIO6_187 0x013a
  205. #define HDMI_CEC 0x013c
  206. #define HDMI_HPD 0x013e
  207. #define HDMI_DDC_SCL 0x0140
  208. #define HDMI_DDC_SDA 0x0142
  209. #define CSIPORTC_LANE0X 0x0144
  210. #define CSIPORTC_LANE0Y 0x0146
  211. #define CSIPORTC_LANE1X 0x0148
  212. #define CSIPORTC_LANE1Y 0x014a
  213. #define CSIPORTB_LANE0X 0x014c
  214. #define CSIPORTB_LANE0Y 0x014e
  215. #define CSIPORTB_LANE1X 0x0150
  216. #define CSIPORTB_LANE1Y 0x0152
  217. #define CSIPORTB_LANE2X 0x0154
  218. #define CSIPORTB_LANE2Y 0x0156
  219. #define CSIPORTA_LANE0X 0x0158
  220. #define CSIPORTA_LANE0Y 0x015a
  221. #define CSIPORTA_LANE1X 0x015c
  222. #define CSIPORTA_LANE1Y 0x015e
  223. #define CSIPORTA_LANE2X 0x0160
  224. #define CSIPORTA_LANE2Y 0x0162
  225. #define CSIPORTA_LANE3X 0x0164
  226. #define CSIPORTA_LANE3Y 0x0166
  227. #define CSIPORTA_LANE4X 0x0168
  228. #define CSIPORTA_LANE4Y 0x016a
  229. #define CAM_SHUTTER 0x016c
  230. #define CAM_STROBE 0x016e
  231. #define CAM_GLOBALRESET 0x0170
  232. #define TIMER11_PWM_EVT 0x0172
  233. #define TIMER5_PWM_EVT 0x0174
  234. #define TIMER6_PWM_EVT 0x0176
  235. #define TIMER8_PWM_EVT 0x0178
  236. #define I2C3_SCL 0x017a
  237. #define I2C3_SDA 0x017c
  238. #define GPIO8_233 0x017e
  239. #define GPIO8_234 0x0180
  240. #define ABE_CLKS 0x0182
  241. #define ABEDMIC_DIN1 0x0184
  242. #define ABEDMIC_DIN2 0x0186
  243. #define ABEDMIC_DIN3 0x0188
  244. #define ABEDMIC_CLK1 0x018a
  245. #define ABEDMIC_CLK2 0x018c
  246. #define ABEDMIC_CLK3 0x018e
  247. #define ABESLIMBUS1_CLOCK 0x0190
  248. #define ABESLIMBUS1_DATA 0x0192
  249. #define ABEMCBSP2_DR 0x0194
  250. #define ABEMCBSP2_DX 0x0196
  251. #define ABEMCBSP2_FSX 0x0198
  252. #define ABEMCBSP2_CLKX 0x019a
  253. #define ABEMCPDM_UL_DATA 0x019c
  254. #define ABEMCPDM_DL_DATA 0x019e
  255. #define ABEMCPDM_FRAME 0x01a0
  256. #define ABEMCPDM_LB_CLK 0x01a2
  257. #define WLSDIO_CLK 0x01a4
  258. #define WLSDIO_CMD 0x01a6
  259. #define WLSDIO_DATA0 0x01a8
  260. #define WLSDIO_DATA1 0x01aa
  261. #define WLSDIO_DATA2 0x01ac
  262. #define WLSDIO_DATA3 0x01ae
  263. #define UART5_RX 0x01b0
  264. #define UART5_TX 0x01b2
  265. #define UART5_CTS 0x01b4
  266. #define UART5_RTS 0x01b6
  267. #define I2C2_SCL 0x01b8
  268. #define I2C2_SDA 0x01ba
  269. #define MCSPI1_CLK 0x01bc
  270. #define MCSPI1_SOMI 0x01be
  271. #define MCSPI1_SIMO 0x01c0
  272. #define MCSPI1_CS0 0x01c2
  273. #define MCSPI1_CS1 0x01c4
  274. #define I2C5_SCL 0x01c6
  275. #define I2C5_SDA 0x01c8
  276. #define PERSLIMBUS2_CLOCK 0x01ca
  277. #define PERSLIMBUS2_DATA 0x01cc
  278. #define UART6_TX 0x01ce
  279. #define UART6_RX 0x01d0
  280. #define UART6_CTS 0x01d2
  281. #define UART6_RTS 0x01d4
  282. #define UART3_CTS_RCTX 0x01d6
  283. #define UART3_RTS_IRSD 0x01d8
  284. #define UART3_TX_IRTX 0x01da
  285. #define UART3_RX_IRRX 0x01dc
  286. #define USBB3_HSIC_STROBE 0x01de
  287. #define USBB3_HSIC_DATA 0x01e0
  288. #define SDCARD_CLK 0x01e2
  289. #define SDCARD_CMD 0x01e4
  290. #define SDCARD_DATA2 0x01e6
  291. #define SDCARD_DATA3 0x01e8
  292. #define SDCARD_DATA0 0x01ea
  293. #define SDCARD_DATA1 0x01ec
  294. #define USBD0_HS_DP 0x01ee
  295. #define USBD0_HS_DM 0x01f0
  296. #define I2C1_PMIC_SCL 0x01f2
  297. #define I2C1_PMIC_SDA 0x01f4
  298. #define USBD0_SS_RX 0x01f6
  299. #define LLIA_WAKEREQIN 0x0040
  300. #define LLIB_WAKEREQIN 0x0042
  301. #define DRM_EMU0 0x0044
  302. #define DRM_EMU1 0x0046
  303. #define JTAG_NTRST 0x0048
  304. #define JTAG_TCK 0x004a
  305. #define JTAG_RTCK 0x004c
  306. #define JTAG_TMSC 0x004e
  307. #define JTAG_TDI 0x0050
  308. #define JTAG_TDO 0x0052
  309. #define SYS_32K 0x0054
  310. #define FREF_CLK_IOREQ 0x0056
  311. #define FREF_CLK0_OUT 0x0058
  312. #define FREF_CLK1_OUT 0x005a
  313. #define FREF_CLK2_OUT 0x005c
  314. #define FREF_CLK2_REQ 0x005e
  315. #define FREF_CLK1_REQ 0x0060
  316. #define SYS_NRESPWRON 0x0062
  317. #define SYS_NRESWARM 0x0064
  318. #define SYS_PWR_REQ 0x0066
  319. #define SYS_NIRQ1 0x0068
  320. #define SYS_NIRQ2 0x006a
  321. #define SR_PMIC_SCL 0x006c
  322. #define SR_PMIC_SDA 0x006e
  323. #define SYS_BOOT0 0x0070
  324. #define SYS_BOOT1 0x0072
  325. #define SYS_BOOT2 0x0074
  326. #define SYS_BOOT3 0x0076
  327. #define SYS_BOOT4 0x0078
  328. #define SYS_BOOT5 0x007a
  329. #endif /* _MUX_OMAP5_H_ */