CU824.h 9.6 KB

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  1. /*
  2. * (C) Copyright 2001-2005
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. *
  25. * Configuration settings for the CU824 board.
  26. *
  27. */
  28. /* ------------------------------------------------------------------------- */
  29. /*
  30. * board/config.h - configuration options, board specific
  31. */
  32. #ifndef __CONFIG_H
  33. #define __CONFIG_H
  34. /*
  35. * High Level Configuration Options
  36. * (easy to change)
  37. */
  38. #define CONFIG_MPC824X 1
  39. #define CONFIG_MPC8240 1
  40. #define CONFIG_CU824 1
  41. #define CONFIG_SYS_TEXT_BASE 0xFFF00000
  42. #define CONFIG_CONS_INDEX 1
  43. #define CONFIG_BAUDRATE 9600
  44. #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  45. #define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
  46. #define CONFIG_BOOTDELAY 5
  47. /*
  48. * BOOTP options
  49. */
  50. #define CONFIG_BOOTP_SUBNETMASK
  51. #define CONFIG_BOOTP_GATEWAY
  52. #define CONFIG_BOOTP_HOSTNAME
  53. #define CONFIG_BOOTP_BOOTPATH
  54. #define CONFIG_BOOTP_BOOTFILESIZE
  55. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  56. /*
  57. * Command line configuration.
  58. */
  59. #include <config_cmd_default.h>
  60. #define CONFIG_CMD_BEDBUG
  61. #define CONFIG_CMD_DHCP
  62. #define CONFIG_CMD_PCI
  63. #define CONFIG_CMD_NFS
  64. #define CONFIG_CMD_SNTP
  65. /*
  66. * Miscellaneous configurable options
  67. */
  68. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  69. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  70. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  71. #if 1
  72. #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
  73. #endif
  74. /* Print Buffer Size
  75. */
  76. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  77. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  78. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  79. #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
  80. /*-----------------------------------------------------------------------
  81. * Start addresses for the final memory configuration
  82. * (Set up by the startup code)
  83. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  84. */
  85. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  86. #define CONFIG_SYS_FLASH_BASE 0xFF000000
  87. #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
  88. #define CONFIG_SYS_EUMB_ADDR 0xFCE00000
  89. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  90. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  91. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  92. #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
  93. #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
  94. /* Maximum amount of RAM.
  95. */
  96. #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
  97. #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
  98. #undef CONFIG_SYS_RAMBOOT
  99. #else
  100. #define CONFIG_SYS_RAMBOOT
  101. #endif
  102. /*-----------------------------------------------------------------------
  103. * Definitions for initial stack pointer and data area
  104. */
  105. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  106. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  107. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  108. /*
  109. * NS16550 Configuration
  110. */
  111. #define CONFIG_SYS_NS16550
  112. #define CONFIG_SYS_NS16550_SERIAL
  113. #define CONFIG_SYS_NS16550_REG_SIZE 4
  114. #define CONFIG_SYS_NS16550_CLK (14745600 / 2)
  115. #define CONFIG_SYS_NS16550_COM1 0xFE800080
  116. #define CONFIG_SYS_NS16550_COM2 0xFE8000C0
  117. /*
  118. * Low Level Configuration Settings
  119. * (address mappings, register initial values, etc.)
  120. * You should know what you are doing if you make changes here.
  121. * For the detail description refer to the MPC8240 user's manual.
  122. */
  123. #define CONFIG_SYS_CLK_FREQ 33000000
  124. #define CONFIG_SYS_HZ 1000
  125. /* Bit-field values for MCCR1.
  126. */
  127. #define CONFIG_SYS_ROMNAL 0
  128. #define CONFIG_SYS_ROMFAL 7
  129. /* Bit-field values for MCCR2.
  130. */
  131. #define CONFIG_SYS_REFINT 430 /* Refresh interval */
  132. /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
  133. */
  134. #define CONFIG_SYS_BSTOPRE 192
  135. /* Bit-field values for MCCR3.
  136. */
  137. #define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
  138. #define CONFIG_SYS_RDLAT 3 /* Data latancy from read command */
  139. /* Bit-field values for MCCR4.
  140. */
  141. #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
  142. #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
  143. #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
  144. #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
  145. #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
  146. #define CONFIG_SYS_ACTORW 2
  147. #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
  148. /* Memory bank settings.
  149. * Only bits 20-29 are actually used from these vales to set the
  150. * start/end addresses. The upper two bits will always be 0, and the lower
  151. * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
  152. * address. Refer to the MPC8240 book.
  153. */
  154. #define CONFIG_SYS_BANK0_START 0x00000000
  155. #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
  156. #define CONFIG_SYS_BANK0_ENABLE 1
  157. #define CONFIG_SYS_BANK1_START 0x3ff00000
  158. #define CONFIG_SYS_BANK1_END 0x3fffffff
  159. #define CONFIG_SYS_BANK1_ENABLE 0
  160. #define CONFIG_SYS_BANK2_START 0x3ff00000
  161. #define CONFIG_SYS_BANK2_END 0x3fffffff
  162. #define CONFIG_SYS_BANK2_ENABLE 0
  163. #define CONFIG_SYS_BANK3_START 0x3ff00000
  164. #define CONFIG_SYS_BANK3_END 0x3fffffff
  165. #define CONFIG_SYS_BANK3_ENABLE 0
  166. #define CONFIG_SYS_BANK4_START 0x3ff00000
  167. #define CONFIG_SYS_BANK4_END 0x3fffffff
  168. #define CONFIG_SYS_BANK4_ENABLE 0
  169. #define CONFIG_SYS_BANK5_START 0x3ff00000
  170. #define CONFIG_SYS_BANK5_END 0x3fffffff
  171. #define CONFIG_SYS_BANK5_ENABLE 0
  172. #define CONFIG_SYS_BANK6_START 0x3ff00000
  173. #define CONFIG_SYS_BANK6_END 0x3fffffff
  174. #define CONFIG_SYS_BANK6_ENABLE 0
  175. #define CONFIG_SYS_BANK7_START 0x3ff00000
  176. #define CONFIG_SYS_BANK7_END 0x3fffffff
  177. #define CONFIG_SYS_BANK7_ENABLE 0
  178. #define CONFIG_SYS_ODCR 0xff
  179. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  180. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  181. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
  182. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  183. #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
  184. #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  185. #define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
  186. #define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
  187. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  188. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  189. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  190. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  191. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  192. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  193. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  194. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  195. /*
  196. * For booting Linux, the board info and command line data
  197. * have to be in the first 8 MB of memory, since this is
  198. * the maximum mapped by the Linux kernel during initialization.
  199. */
  200. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  201. /*-----------------------------------------------------------------------
  202. * FLASH organization
  203. */
  204. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */
  205. #define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
  206. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  207. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  208. /* Warining: environment is not EMBEDDED in the U-Boot code.
  209. * It's stored in flash separately.
  210. */
  211. #define CONFIG_ENV_IS_IN_FLASH 1
  212. #if 0
  213. #define CONFIG_ENV_ADDR 0xFF008000
  214. #define CONFIG_ENV_SIZE 0x8000 /* Size of the Environment Sector */
  215. #else
  216. #define CONFIG_ENV_ADDR 0xFFFC0000
  217. #define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
  218. #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
  219. #define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
  220. #endif
  221. /*-----------------------------------------------------------------------
  222. * Cache Configuration
  223. */
  224. #define CONFIG_SYS_CACHELINE_SIZE 32
  225. #if defined(CONFIG_CMD_KGDB)
  226. # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  227. #endif
  228. /*-----------------------------------------------------------------------
  229. * PCI stuff
  230. *-----------------------------------------------------------------------
  231. */
  232. #define CONFIG_PCI /* include pci support */
  233. #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  234. #undef CONFIG_PCI_PNP
  235. #define CONFIG_TULIP
  236. #define CONFIG_TULIP_USE_IO
  237. #define CONFIG_SYS_ETH_DEV_FN 0x7800
  238. #define CONFIG_SYS_ETH_IOBASE 0x00104000
  239. #define CONFIG_EEPRO100
  240. #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
  241. #define PCI_ENET0_IOADDR 0x00104000
  242. #define PCI_ENET0_MEMADDR 0x80000000
  243. #endif /* __CONFIG_H */