woodburn.c 6.2 KB

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  1. /*
  2. * Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
  3. *
  4. * Based on flea3.c and mx35pdk.c
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #include <common.h>
  25. #include <asm/io.h>
  26. #include <asm/errno.h>
  27. #include <asm/arch/imx-regs.h>
  28. #include <asm/arch/crm_regs.h>
  29. #include <asm/arch/clock.h>
  30. #include <asm/arch/iomux-mx35.h>
  31. #include <i2c.h>
  32. #include <power/pmic.h>
  33. #include <fsl_pmic.h>
  34. #include <mc13892.h>
  35. #include <mmc.h>
  36. #include <fsl_esdhc.h>
  37. #include <linux/types.h>
  38. #include <asm/gpio.h>
  39. #include <asm/arch/sys_proto.h>
  40. #include <netdev.h>
  41. #include <spl.h>
  42. #define CCM_CCMR_CONFIG 0x003F4208
  43. #define ESDCTL_DDR2_CONFIG 0x007FFC3F
  44. /* For MMC */
  45. #define GPIO_MMC_CD 7
  46. #define GPIO_MMC_WP 8
  47. DECLARE_GLOBAL_DATA_PTR;
  48. int dram_init(void)
  49. {
  50. gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
  51. PHYS_SDRAM_1_SIZE);
  52. return 0;
  53. }
  54. static void board_setup_sdram(void)
  55. {
  56. struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
  57. /* Initialize with default values both CSD0/1 */
  58. writel(0x2000, &esdc->esdctl0);
  59. writel(0x2000, &esdc->esdctl1);
  60. mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
  61. 13, 10, 2, 0x8080);
  62. }
  63. static void setup_iomux_fec(void)
  64. {
  65. static const iomux_v3_cfg_t fec_pads[] = {
  66. MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
  67. MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
  68. MX35_PAD_FEC_RX_DV__FEC_RX_DV,
  69. MX35_PAD_FEC_COL__FEC_COL,
  70. MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
  71. MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
  72. MX35_PAD_FEC_TX_EN__FEC_TX_EN,
  73. MX35_PAD_FEC_MDC__FEC_MDC,
  74. MX35_PAD_FEC_MDIO__FEC_MDIO,
  75. MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
  76. MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
  77. MX35_PAD_FEC_CRS__FEC_CRS,
  78. MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
  79. MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
  80. MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
  81. MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
  82. MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
  83. MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
  84. };
  85. /* setup pins for FEC */
  86. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  87. }
  88. int woodburn_init(void)
  89. {
  90. struct ccm_regs *ccm =
  91. (struct ccm_regs *)IMX_CCM_BASE;
  92. /* initialize PLL and clock configuration */
  93. writel(CCM_CCMR_CONFIG, &ccm->ccmr);
  94. /* Set-up RAM */
  95. board_setup_sdram();
  96. /* enable clocks */
  97. writel(readl(&ccm->cgr0) |
  98. MXC_CCM_CGR0_EMI_MASK |
  99. MXC_CCM_CGR0_EDIO_MASK |
  100. MXC_CCM_CGR0_EPIT1_MASK,
  101. &ccm->cgr0);
  102. writel(readl(&ccm->cgr1) |
  103. MXC_CCM_CGR1_FEC_MASK |
  104. MXC_CCM_CGR1_GPIO1_MASK |
  105. MXC_CCM_CGR1_GPIO2_MASK |
  106. MXC_CCM_CGR1_GPIO3_MASK |
  107. MXC_CCM_CGR1_I2C1_MASK |
  108. MXC_CCM_CGR1_I2C2_MASK |
  109. MXC_CCM_CGR1_I2C3_MASK,
  110. &ccm->cgr1);
  111. /* Set-up NAND */
  112. __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
  113. /* Set pinmux for the required peripherals */
  114. setup_iomux_fec();
  115. /* setup GPIO1_4 FEC_ENABLE signal */
  116. imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4);
  117. gpio_direction_output(4, 1);
  118. imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9);
  119. gpio_direction_output(9, 1);
  120. return 0;
  121. }
  122. #if defined(CONFIG_SPL_BUILD)
  123. void board_init_f(ulong dummy)
  124. {
  125. /* Set the stack pointer. */
  126. asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
  127. /* Initialize MUX and SDRAM */
  128. woodburn_init();
  129. /* Clear the BSS. */
  130. memset(__bss_start, 0, __bss_end - __bss_start);
  131. /* Set global data pointer. */
  132. gd = &gdata;
  133. preloader_console_init();
  134. timer_init();
  135. board_init_r(NULL, 0);
  136. }
  137. void spl_board_init(void)
  138. {
  139. }
  140. #endif
  141. /* Booting from NOR in external mode */
  142. int board_early_init_f(void)
  143. {
  144. return woodburn_init();
  145. }
  146. int board_init(void)
  147. {
  148. struct pmic *p;
  149. u32 val;
  150. int ret;
  151. /* address of boot parameters */
  152. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  153. ret = pmic_init(I2C_PMIC);
  154. if (ret)
  155. return ret;
  156. p = pmic_get("FSL_PMIC");
  157. /*
  158. * Set switchers in Auto in NORMAL mode & STANDBY mode
  159. * Setup the switcher mode for SW1 & SW2
  160. */
  161. pmic_reg_read(p, REG_SW_4, &val);
  162. val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
  163. (SWMODE_MASK << SWMODE2_SHIFT)));
  164. val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
  165. (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
  166. /* Set SWILIMB */
  167. val |= (1 << 22);
  168. pmic_reg_write(p, REG_SW_4, val);
  169. /* Setup the switcher mode for SW3 & SW4 */
  170. pmic_reg_read(p, REG_SW_5, &val);
  171. val &= ~((SWMODE_MASK << SWMODE4_SHIFT) |
  172. (SWMODE_MASK << SWMODE3_SHIFT));
  173. val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) |
  174. (SWMODE_AUTO_AUTO << SWMODE3_SHIFT);
  175. pmic_reg_write(p, REG_SW_5, val);
  176. /* Set VGEN1 to 3.15V */
  177. pmic_reg_read(p, REG_SETTING_0, &val);
  178. val &= ~(VGEN1_MASK);
  179. val |= VGEN1_3_15;
  180. pmic_reg_write(p, REG_SETTING_0, val);
  181. pmic_reg_read(p, REG_MODE_0, &val);
  182. val |= VGEN1EN;
  183. pmic_reg_write(p, REG_MODE_0, val);
  184. udelay(2000);
  185. return 0;
  186. }
  187. #if defined(CONFIG_FSL_ESDHC)
  188. struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
  189. int board_mmc_init(bd_t *bis)
  190. {
  191. static const iomux_v3_cfg_t sdhc1_pads[] = {
  192. MX35_PAD_SD1_CMD__ESDHC1_CMD,
  193. MX35_PAD_SD1_CLK__ESDHC1_CLK,
  194. MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
  195. MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
  196. MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
  197. MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
  198. };
  199. /* configure pins for SDHC1 only */
  200. imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
  201. /* MMC Card Detect on GPIO1_7 */
  202. imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7);
  203. gpio_direction_input(GPIO_MMC_CD);
  204. /* MMC Write Protection on GPIO1_8 */
  205. imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8);
  206. gpio_direction_input(GPIO_MMC_WP);
  207. esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  208. return fsl_esdhc_initialize(bis, &esdhc_cfg);
  209. }
  210. int board_mmc_getcd(struct mmc *mmc)
  211. {
  212. return !gpio_get_value(GPIO_MMC_CD);
  213. }
  214. #endif
  215. u32 get_board_rev(void)
  216. {
  217. int rev = 0;
  218. return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  219. }