s3c_udc_otg.c 21 KB

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  1. /*
  2. * drivers/usb/gadget/s3c_udc_otg.c
  3. * Samsung S3C on-chip full/high speed USB OTG 2.0 device controllers
  4. *
  5. * Copyright (C) 2008 for Samsung Electronics
  6. *
  7. * BSP Support for Samsung's UDC driver
  8. * available at:
  9. * git://git.kernel.org/pub/scm/linux/kernel/git/kki_ap/linux-2.6-samsung.git
  10. *
  11. * State machine bugfixes:
  12. * Marek Szyprowski <m.szyprowski@samsung.com>
  13. *
  14. * Ported to u-boot:
  15. * Marek Szyprowski <m.szyprowski@samsung.com>
  16. * Lukasz Majewski <l.majewski@samsumg.com>
  17. *
  18. * This program is free software; you can redistribute it and/or modify
  19. * it under the terms of the GNU General Public License as published by
  20. * the Free Software Foundation; either version 2 of the License, or
  21. * (at your option) any later version.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  31. *
  32. */
  33. #undef DEBUG
  34. #include <common.h>
  35. #include <asm/errno.h>
  36. #include <linux/list.h>
  37. #include <malloc.h>
  38. #include <linux/usb/ch9.h>
  39. #include <linux/usb/gadget.h>
  40. #include <asm/byteorder.h>
  41. #include <asm/unaligned.h>
  42. #include <asm/io.h>
  43. #include <asm/mach-types.h>
  44. #include <asm/arch/gpio.h>
  45. #include "regs-otg.h"
  46. #include <usb/lin_gadget_compat.h>
  47. /***********************************************************/
  48. #define OTG_DMA_MODE 1
  49. #define DEBUG_SETUP 0
  50. #define DEBUG_EP0 0
  51. #define DEBUG_ISR 0
  52. #define DEBUG_OUT_EP 0
  53. #define DEBUG_IN_EP 0
  54. #include <usb/s3c_udc.h>
  55. #define EP0_CON 0
  56. #define EP_MASK 0xF
  57. static char *state_names[] = {
  58. "WAIT_FOR_SETUP",
  59. "DATA_STATE_XMIT",
  60. "DATA_STATE_NEED_ZLP",
  61. "WAIT_FOR_OUT_STATUS",
  62. "DATA_STATE_RECV",
  63. "WAIT_FOR_COMPLETE",
  64. "WAIT_FOR_OUT_COMPLETE",
  65. "WAIT_FOR_IN_COMPLETE",
  66. "WAIT_FOR_NULL_COMPLETE",
  67. };
  68. #define DRIVER_DESC "S3C HS USB OTG Device Driver, (c) Samsung Electronics"
  69. #define DRIVER_VERSION "15 March 2009"
  70. struct s3c_udc *the_controller;
  71. static const char driver_name[] = "s3c-udc";
  72. static const char driver_desc[] = DRIVER_DESC;
  73. static const char ep0name[] = "ep0-control";
  74. /* Max packet size*/
  75. static unsigned int ep0_fifo_size = 64;
  76. static unsigned int ep_fifo_size = 512;
  77. static unsigned int ep_fifo_size2 = 1024;
  78. static int reset_available = 1;
  79. static struct usb_ctrlrequest *usb_ctrl;
  80. static dma_addr_t usb_ctrl_dma_addr;
  81. /*
  82. Local declarations.
  83. */
  84. static int s3c_ep_enable(struct usb_ep *ep,
  85. const struct usb_endpoint_descriptor *);
  86. static int s3c_ep_disable(struct usb_ep *ep);
  87. static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
  88. gfp_t gfp_flags);
  89. static void s3c_free_request(struct usb_ep *ep, struct usb_request *);
  90. static int s3c_queue(struct usb_ep *ep, struct usb_request *, gfp_t gfp_flags);
  91. static int s3c_dequeue(struct usb_ep *ep, struct usb_request *);
  92. static int s3c_fifo_status(struct usb_ep *ep);
  93. static void s3c_fifo_flush(struct usb_ep *ep);
  94. static void s3c_ep0_read(struct s3c_udc *dev);
  95. static void s3c_ep0_kick(struct s3c_udc *dev, struct s3c_ep *ep);
  96. static void s3c_handle_ep0(struct s3c_udc *dev);
  97. static int s3c_ep0_write(struct s3c_udc *dev);
  98. static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req);
  99. static void done(struct s3c_ep *ep, struct s3c_request *req, int status);
  100. static void stop_activity(struct s3c_udc *dev,
  101. struct usb_gadget_driver *driver);
  102. static int udc_enable(struct s3c_udc *dev);
  103. static void udc_set_address(struct s3c_udc *dev, unsigned char address);
  104. static void reconfig_usbd(void);
  105. static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed);
  106. static void nuke(struct s3c_ep *ep, int status);
  107. static int s3c_udc_set_halt(struct usb_ep *_ep, int value);
  108. static void s3c_udc_set_nak(struct s3c_ep *ep);
  109. void set_udc_gadget_private_data(void *p)
  110. {
  111. debug_cond(DEBUG_SETUP != 0,
  112. "%s: the_controller: 0x%p, p: 0x%p\n", __func__,
  113. the_controller, p);
  114. the_controller->gadget.dev.device_data = p;
  115. }
  116. void *get_udc_gadget_private_data(struct usb_gadget *gadget)
  117. {
  118. return gadget->dev.device_data;
  119. }
  120. static struct usb_ep_ops s3c_ep_ops = {
  121. .enable = s3c_ep_enable,
  122. .disable = s3c_ep_disable,
  123. .alloc_request = s3c_alloc_request,
  124. .free_request = s3c_free_request,
  125. .queue = s3c_queue,
  126. .dequeue = s3c_dequeue,
  127. .set_halt = s3c_udc_set_halt,
  128. .fifo_status = s3c_fifo_status,
  129. .fifo_flush = s3c_fifo_flush,
  130. };
  131. #define create_proc_files() do {} while (0)
  132. #define remove_proc_files() do {} while (0)
  133. /***********************************************************/
  134. void __iomem *regs_otg;
  135. struct s3c_usbotg_reg *reg;
  136. struct s3c_usbotg_phy *phy;
  137. static unsigned int usb_phy_ctrl;
  138. void otg_phy_init(struct s3c_udc *dev)
  139. {
  140. dev->pdata->phy_control(1);
  141. /*USB PHY0 Enable */
  142. printf("USB PHY0 Enable\n");
  143. /* Enable PHY */
  144. writel(readl(usb_phy_ctrl) | USB_PHY_CTRL_EN0, usb_phy_ctrl);
  145. if (dev->pdata->usb_flags == PHY0_SLEEP) /* C210 Universal */
  146. writel((readl(&phy->phypwr)
  147. &~(PHY_0_SLEEP | OTG_DISABLE_0 | ANALOG_PWRDOWN)
  148. &~FORCE_SUSPEND_0), &phy->phypwr);
  149. else /* C110 GONI */
  150. writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
  151. &~FORCE_SUSPEND_0), &phy->phypwr);
  152. writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
  153. CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
  154. writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
  155. | PHY_SW_RST0, &phy->rstcon);
  156. udelay(10);
  157. writel(readl(&phy->rstcon)
  158. &~(PHY_SW_RST0 | LINK_SW_RST | PHYLNK_SW_RST), &phy->rstcon);
  159. udelay(10);
  160. }
  161. void otg_phy_off(struct s3c_udc *dev)
  162. {
  163. /* reset controller just in case */
  164. writel(PHY_SW_RST0, &phy->rstcon);
  165. udelay(20);
  166. writel(readl(&phy->phypwr) &~PHY_SW_RST0, &phy->rstcon);
  167. udelay(20);
  168. writel(readl(&phy->phypwr) | OTG_DISABLE_0 | ANALOG_PWRDOWN
  169. | FORCE_SUSPEND_0, &phy->phypwr);
  170. writel(readl(usb_phy_ctrl) &~USB_PHY_CTRL_EN0, usb_phy_ctrl);
  171. writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)),
  172. &phy->phyclk);
  173. udelay(10000);
  174. dev->pdata->phy_control(0);
  175. }
  176. /***********************************************************/
  177. #include "s3c_udc_otg_xfer_dma.c"
  178. /*
  179. * udc_disable - disable USB device controller
  180. */
  181. static void udc_disable(struct s3c_udc *dev)
  182. {
  183. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  184. udc_set_address(dev, 0);
  185. dev->ep0state = WAIT_FOR_SETUP;
  186. dev->gadget.speed = USB_SPEED_UNKNOWN;
  187. dev->usb_address = 0;
  188. otg_phy_off(dev);
  189. }
  190. /*
  191. * udc_reinit - initialize software state
  192. */
  193. static void udc_reinit(struct s3c_udc *dev)
  194. {
  195. unsigned int i;
  196. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  197. /* device/ep0 records init */
  198. INIT_LIST_HEAD(&dev->gadget.ep_list);
  199. INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
  200. dev->ep0state = WAIT_FOR_SETUP;
  201. /* basic endpoint records init */
  202. for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
  203. struct s3c_ep *ep = &dev->ep[i];
  204. if (i != 0)
  205. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  206. ep->desc = 0;
  207. ep->stopped = 0;
  208. INIT_LIST_HEAD(&ep->queue);
  209. ep->pio_irqs = 0;
  210. }
  211. /* the rest was statically initialized, and is read-only */
  212. }
  213. #define BYTES2MAXP(x) (x / 8)
  214. #define MAXP2BYTES(x) (x * 8)
  215. /* until it's enabled, this UDC should be completely invisible
  216. * to any USB host.
  217. */
  218. static int udc_enable(struct s3c_udc *dev)
  219. {
  220. debug_cond(DEBUG_SETUP != 0, "%s: %p\n", __func__, dev);
  221. otg_phy_init(dev);
  222. reconfig_usbd();
  223. debug_cond(DEBUG_SETUP != 0,
  224. "S3C USB 2.0 OTG Controller Core Initialized : 0x%x\n",
  225. readl(&reg->gintmsk));
  226. dev->gadget.speed = USB_SPEED_UNKNOWN;
  227. return 0;
  228. }
  229. /*
  230. Register entry point for the peripheral controller driver.
  231. */
  232. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  233. {
  234. struct s3c_udc *dev = the_controller;
  235. int retval = 0;
  236. unsigned long flags;
  237. debug_cond(DEBUG_SETUP != 0, "%s: %s\n", __func__, "no name");
  238. if (!driver
  239. || (driver->speed != USB_SPEED_FULL
  240. && driver->speed != USB_SPEED_HIGH)
  241. || !driver->bind || !driver->disconnect || !driver->setup)
  242. return -EINVAL;
  243. if (!dev)
  244. return -ENODEV;
  245. if (dev->driver)
  246. return -EBUSY;
  247. spin_lock_irqsave(&dev->lock, flags);
  248. /* first hook up the driver ... */
  249. dev->driver = driver;
  250. spin_unlock_irqrestore(&dev->lock, flags);
  251. if (retval) { /* TODO */
  252. printf("target device_add failed, error %d\n", retval);
  253. return retval;
  254. }
  255. retval = driver->bind(&dev->gadget);
  256. if (retval) {
  257. debug_cond(DEBUG_SETUP != 0,
  258. "%s: bind to driver --> error %d\n",
  259. dev->gadget.name, retval);
  260. dev->driver = 0;
  261. return retval;
  262. }
  263. enable_irq(IRQ_OTG);
  264. debug_cond(DEBUG_SETUP != 0,
  265. "Registered gadget driver %s\n", dev->gadget.name);
  266. udc_enable(dev);
  267. return 0;
  268. }
  269. /*
  270. * Unregister entry point for the peripheral controller driver.
  271. */
  272. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  273. {
  274. struct s3c_udc *dev = the_controller;
  275. unsigned long flags;
  276. if (!dev)
  277. return -ENODEV;
  278. if (!driver || driver != dev->driver)
  279. return -EINVAL;
  280. spin_lock_irqsave(&dev->lock, flags);
  281. dev->driver = 0;
  282. stop_activity(dev, driver);
  283. spin_unlock_irqrestore(&dev->lock, flags);
  284. driver->unbind(&dev->gadget);
  285. disable_irq(IRQ_OTG);
  286. udc_disable(dev);
  287. return 0;
  288. }
  289. /*
  290. * done - retire a request; caller blocked irqs
  291. */
  292. static void done(struct s3c_ep *ep, struct s3c_request *req, int status)
  293. {
  294. unsigned int stopped = ep->stopped;
  295. debug("%s: %s %p, req = %p, stopped = %d\n",
  296. __func__, ep->ep.name, ep, &req->req, stopped);
  297. list_del_init(&req->queue);
  298. if (likely(req->req.status == -EINPROGRESS))
  299. req->req.status = status;
  300. else
  301. status = req->req.status;
  302. if (status && status != -ESHUTDOWN) {
  303. debug("complete %s req %p stat %d len %u/%u\n",
  304. ep->ep.name, &req->req, status,
  305. req->req.actual, req->req.length);
  306. }
  307. /* don't modify queue heads during completion callback */
  308. ep->stopped = 1;
  309. #ifdef DEBUG
  310. printf("calling complete callback\n");
  311. {
  312. int i, len = req->req.length;
  313. printf("pkt[%d] = ", req->req.length);
  314. if (len > 64)
  315. len = 64;
  316. for (i = 0; i < len; i++) {
  317. printf("%02x", ((u8 *)req->req.buf)[i]);
  318. if ((i & 7) == 7)
  319. printf(" ");
  320. }
  321. printf("\n");
  322. }
  323. #endif
  324. spin_unlock(&ep->dev->lock);
  325. req->req.complete(&ep->ep, &req->req);
  326. spin_lock(&ep->dev->lock);
  327. debug("callback completed\n");
  328. ep->stopped = stopped;
  329. }
  330. /*
  331. * nuke - dequeue ALL requests
  332. */
  333. static void nuke(struct s3c_ep *ep, int status)
  334. {
  335. struct s3c_request *req;
  336. debug("%s: %s %p\n", __func__, ep->ep.name, ep);
  337. /* called with irqs blocked */
  338. while (!list_empty(&ep->queue)) {
  339. req = list_entry(ep->queue.next, struct s3c_request, queue);
  340. done(ep, req, status);
  341. }
  342. }
  343. static void stop_activity(struct s3c_udc *dev,
  344. struct usb_gadget_driver *driver)
  345. {
  346. int i;
  347. /* don't disconnect drivers more than once */
  348. if (dev->gadget.speed == USB_SPEED_UNKNOWN)
  349. driver = 0;
  350. dev->gadget.speed = USB_SPEED_UNKNOWN;
  351. /* prevent new request submissions, kill any outstanding requests */
  352. for (i = 0; i < S3C_MAX_ENDPOINTS; i++) {
  353. struct s3c_ep *ep = &dev->ep[i];
  354. ep->stopped = 1;
  355. nuke(ep, -ESHUTDOWN);
  356. }
  357. /* report disconnect; the driver is already quiesced */
  358. if (driver) {
  359. spin_unlock(&dev->lock);
  360. driver->disconnect(&dev->gadget);
  361. spin_lock(&dev->lock);
  362. }
  363. /* re-init driver-visible data structures */
  364. udc_reinit(dev);
  365. }
  366. static void reconfig_usbd(void)
  367. {
  368. /* 2. Soft-reset OTG Core and then unreset again. */
  369. int i;
  370. unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
  371. debug("Reseting OTG controller\n");
  372. writel(0<<15 /* PHY Low Power Clock sel*/
  373. |1<<14 /* Non-Periodic TxFIFO Rewind Enable*/
  374. |0x5<<10 /* Turnaround time*/
  375. |0<<9 | 0<<8 /* [0:HNP disable,1:HNP enable][ 0:SRP disable*/
  376. /* 1:SRP enable] H1= 1,1*/
  377. |0<<7 /* Ulpi DDR sel*/
  378. |0<<6 /* 0: high speed utmi+, 1: full speed serial*/
  379. |0<<4 /* 0: utmi+, 1:ulpi*/
  380. |1<<3 /* phy i/f 0:8bit, 1:16bit*/
  381. |0x7<<0, /* HS/FS Timeout**/
  382. &reg->gusbcfg);
  383. /* 3. Put the OTG device core in the disconnected state.*/
  384. uTemp = readl(&reg->dctl);
  385. uTemp |= SOFT_DISCONNECT;
  386. writel(uTemp, &reg->dctl);
  387. udelay(20);
  388. /* 4. Make the OTG device core exit from the disconnected state.*/
  389. uTemp = readl(&reg->dctl);
  390. uTemp = uTemp & ~SOFT_DISCONNECT;
  391. writel(uTemp, &reg->dctl);
  392. /* 5. Configure OTG Core to initial settings of device mode.*/
  393. /* [][1: full speed(30Mhz) 0:high speed]*/
  394. writel(EP_MISS_CNT(1) | DEV_SPEED_HIGH_SPEED_20, &reg->dcfg);
  395. mdelay(1);
  396. /* 6. Unmask the core interrupts*/
  397. writel(GINTMSK_INIT, &reg->gintmsk);
  398. /* 7. Set NAK bit of EP0, EP1, EP2*/
  399. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[EP0_CON].doepctl);
  400. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[EP0_CON].diepctl);
  401. for (i = 1; i < S3C_MAX_ENDPOINTS; i++) {
  402. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->out_endp[i].doepctl);
  403. writel(DEPCTL_EPDIS|DEPCTL_SNAK, &reg->in_endp[i].diepctl);
  404. }
  405. /* 8. Unmask EPO interrupts*/
  406. writel(((1 << EP0_CON) << DAINT_OUT_BIT)
  407. | (1 << EP0_CON), &reg->daintmsk);
  408. /* 9. Unmask device OUT EP common interrupts*/
  409. writel(DOEPMSK_INIT, &reg->doepmsk);
  410. /* 10. Unmask device IN EP common interrupts*/
  411. writel(DIEPMSK_INIT, &reg->diepmsk);
  412. /* 11. Set Rx FIFO Size (in 32-bit words) */
  413. writel(RX_FIFO_SIZE >> 2, &reg->grxfsiz);
  414. /* 12. Set Non Periodic Tx FIFO Size */
  415. writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0,
  416. &reg->gnptxfsiz);
  417. for (i = 1; i < S3C_MAX_HW_ENDPOINTS; i++)
  418. writel((PTX_FIFO_SIZE >> 2) << 16 |
  419. ((RX_FIFO_SIZE + NPTX_FIFO_SIZE +
  420. PTX_FIFO_SIZE*(i-1)) >> 2) << 0,
  421. &reg->dieptxf[i-1]);
  422. /* Flush the RX FIFO */
  423. writel(RX_FIFO_FLUSH, &reg->grstctl);
  424. while (readl(&reg->grstctl) & RX_FIFO_FLUSH)
  425. debug("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
  426. /* Flush all the Tx FIFO's */
  427. writel(TX_FIFO_FLUSH_ALL, &reg->grstctl);
  428. writel(TX_FIFO_FLUSH_ALL | TX_FIFO_FLUSH, &reg->grstctl);
  429. while (readl(&reg->grstctl) & TX_FIFO_FLUSH)
  430. debug("%s: waiting for S3C_UDC_OTG_GRSTCTL\n", __func__);
  431. /* 13. Clear NAK bit of EP0, EP1, EP2*/
  432. /* For Slave mode*/
  433. /* EP0: Control OUT */
  434. writel(DEPCTL_EPDIS | DEPCTL_CNAK,
  435. &reg->out_endp[EP0_CON].doepctl);
  436. /* 14. Initialize OTG Link Core.*/
  437. writel(GAHBCFG_INIT, &reg->gahbcfg);
  438. }
  439. static void set_max_pktsize(struct s3c_udc *dev, enum usb_device_speed speed)
  440. {
  441. unsigned int ep_ctrl;
  442. int i;
  443. if (speed == USB_SPEED_HIGH) {
  444. ep0_fifo_size = 64;
  445. ep_fifo_size = 512;
  446. ep_fifo_size2 = 1024;
  447. dev->gadget.speed = USB_SPEED_HIGH;
  448. } else {
  449. ep0_fifo_size = 64;
  450. ep_fifo_size = 64;
  451. ep_fifo_size2 = 64;
  452. dev->gadget.speed = USB_SPEED_FULL;
  453. }
  454. dev->ep[0].ep.maxpacket = ep0_fifo_size;
  455. for (i = 1; i < S3C_MAX_ENDPOINTS; i++)
  456. dev->ep[i].ep.maxpacket = ep_fifo_size;
  457. /* EP0 - Control IN (64 bytes)*/
  458. ep_ctrl = readl(&reg->in_endp[EP0_CON].diepctl);
  459. writel(ep_ctrl|(0<<0), &reg->in_endp[EP0_CON].diepctl);
  460. /* EP0 - Control OUT (64 bytes)*/
  461. ep_ctrl = readl(&reg->out_endp[EP0_CON].doepctl);
  462. writel(ep_ctrl|(0<<0), &reg->out_endp[EP0_CON].doepctl);
  463. }
  464. static int s3c_ep_enable(struct usb_ep *_ep,
  465. const struct usb_endpoint_descriptor *desc)
  466. {
  467. struct s3c_ep *ep;
  468. struct s3c_udc *dev;
  469. unsigned long flags;
  470. debug("%s: %p\n", __func__, _ep);
  471. ep = container_of(_ep, struct s3c_ep, ep);
  472. if (!_ep || !desc || ep->desc || _ep->name == ep0name
  473. || desc->bDescriptorType != USB_DT_ENDPOINT
  474. || ep->bEndpointAddress != desc->bEndpointAddress
  475. || ep_maxpacket(ep) <
  476. le16_to_cpu(get_unaligned(&desc->wMaxPacketSize))) {
  477. debug("%s: bad ep or descriptor\n", __func__);
  478. return -EINVAL;
  479. }
  480. /* xfer types must match, except that interrupt ~= bulk */
  481. if (ep->bmAttributes != desc->bmAttributes
  482. && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
  483. && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
  484. debug("%s: %s type mismatch\n", __func__, _ep->name);
  485. return -EINVAL;
  486. }
  487. /* hardware _could_ do smaller, but driver doesn't */
  488. if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
  489. && le16_to_cpu(get_unaligned(&desc->wMaxPacketSize)) !=
  490. ep_maxpacket(ep)) || !get_unaligned(&desc->wMaxPacketSize)) {
  491. debug("%s: bad %s maxpacket\n", __func__, _ep->name);
  492. return -ERANGE;
  493. }
  494. dev = ep->dev;
  495. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
  496. debug("%s: bogus device state\n", __func__);
  497. return -ESHUTDOWN;
  498. }
  499. ep->stopped = 0;
  500. ep->desc = desc;
  501. ep->pio_irqs = 0;
  502. ep->ep.maxpacket = le16_to_cpu(get_unaligned(&desc->wMaxPacketSize));
  503. /* Reset halt state */
  504. s3c_udc_set_nak(ep);
  505. s3c_udc_set_halt(_ep, 0);
  506. spin_lock_irqsave(&ep->dev->lock, flags);
  507. s3c_udc_ep_activate(ep);
  508. spin_unlock_irqrestore(&ep->dev->lock, flags);
  509. debug("%s: enabled %s, stopped = %d, maxpacket = %d\n",
  510. __func__, _ep->name, ep->stopped, ep->ep.maxpacket);
  511. return 0;
  512. }
  513. /*
  514. * Disable EP
  515. */
  516. static int s3c_ep_disable(struct usb_ep *_ep)
  517. {
  518. struct s3c_ep *ep;
  519. unsigned long flags;
  520. debug("%s: %p\n", __func__, _ep);
  521. ep = container_of(_ep, struct s3c_ep, ep);
  522. if (!_ep || !ep->desc) {
  523. debug("%s: %s not enabled\n", __func__,
  524. _ep ? ep->ep.name : NULL);
  525. return -EINVAL;
  526. }
  527. spin_lock_irqsave(&ep->dev->lock, flags);
  528. /* Nuke all pending requests */
  529. nuke(ep, -ESHUTDOWN);
  530. ep->desc = 0;
  531. ep->stopped = 1;
  532. spin_unlock_irqrestore(&ep->dev->lock, flags);
  533. debug("%s: disabled %s\n", __func__, _ep->name);
  534. return 0;
  535. }
  536. static struct usb_request *s3c_alloc_request(struct usb_ep *ep,
  537. gfp_t gfp_flags)
  538. {
  539. struct s3c_request *req;
  540. debug("%s: %s %p\n", __func__, ep->name, ep);
  541. req = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*req));
  542. if (!req)
  543. return 0;
  544. memset(req, 0, sizeof *req);
  545. INIT_LIST_HEAD(&req->queue);
  546. return &req->req;
  547. }
  548. static void s3c_free_request(struct usb_ep *ep, struct usb_request *_req)
  549. {
  550. struct s3c_request *req;
  551. debug("%s: %p\n", __func__, ep);
  552. req = container_of(_req, struct s3c_request, req);
  553. WARN_ON(!list_empty(&req->queue));
  554. kfree(req);
  555. }
  556. /* dequeue JUST ONE request */
  557. static int s3c_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  558. {
  559. struct s3c_ep *ep;
  560. struct s3c_request *req;
  561. unsigned long flags;
  562. debug("%s: %p\n", __func__, _ep);
  563. ep = container_of(_ep, struct s3c_ep, ep);
  564. if (!_ep || ep->ep.name == ep0name)
  565. return -EINVAL;
  566. spin_lock_irqsave(&ep->dev->lock, flags);
  567. /* make sure it's actually queued on this endpoint */
  568. list_for_each_entry(req, &ep->queue, queue) {
  569. if (&req->req == _req)
  570. break;
  571. }
  572. if (&req->req != _req) {
  573. spin_unlock_irqrestore(&ep->dev->lock, flags);
  574. return -EINVAL;
  575. }
  576. done(ep, req, -ECONNRESET);
  577. spin_unlock_irqrestore(&ep->dev->lock, flags);
  578. return 0;
  579. }
  580. /*
  581. * Return bytes in EP FIFO
  582. */
  583. static int s3c_fifo_status(struct usb_ep *_ep)
  584. {
  585. int count = 0;
  586. struct s3c_ep *ep;
  587. ep = container_of(_ep, struct s3c_ep, ep);
  588. if (!_ep) {
  589. debug("%s: bad ep\n", __func__);
  590. return -ENODEV;
  591. }
  592. debug("%s: %d\n", __func__, ep_index(ep));
  593. /* LPD can't report unclaimed bytes from IN fifos */
  594. if (ep_is_in(ep))
  595. return -EOPNOTSUPP;
  596. return count;
  597. }
  598. /*
  599. * Flush EP FIFO
  600. */
  601. static void s3c_fifo_flush(struct usb_ep *_ep)
  602. {
  603. struct s3c_ep *ep;
  604. ep = container_of(_ep, struct s3c_ep, ep);
  605. if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
  606. debug("%s: bad ep\n", __func__);
  607. return;
  608. }
  609. debug("%s: %d\n", __func__, ep_index(ep));
  610. }
  611. static const struct usb_gadget_ops s3c_udc_ops = {
  612. /* current versions must always be self-powered */
  613. };
  614. static struct s3c_udc memory = {
  615. .usb_address = 0,
  616. .gadget = {
  617. .ops = &s3c_udc_ops,
  618. .ep0 = &memory.ep[0].ep,
  619. .name = driver_name,
  620. },
  621. /* control endpoint */
  622. .ep[0] = {
  623. .ep = {
  624. .name = ep0name,
  625. .ops = &s3c_ep_ops,
  626. .maxpacket = EP0_FIFO_SIZE,
  627. },
  628. .dev = &memory,
  629. .bEndpointAddress = 0,
  630. .bmAttributes = 0,
  631. .ep_type = ep_control,
  632. },
  633. /* first group of endpoints */
  634. .ep[1] = {
  635. .ep = {
  636. .name = "ep1in-bulk",
  637. .ops = &s3c_ep_ops,
  638. .maxpacket = EP_FIFO_SIZE,
  639. },
  640. .dev = &memory,
  641. .bEndpointAddress = USB_DIR_IN | 1,
  642. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  643. .ep_type = ep_bulk_out,
  644. .fifo_num = 1,
  645. },
  646. .ep[2] = {
  647. .ep = {
  648. .name = "ep2out-bulk",
  649. .ops = &s3c_ep_ops,
  650. .maxpacket = EP_FIFO_SIZE,
  651. },
  652. .dev = &memory,
  653. .bEndpointAddress = USB_DIR_OUT | 2,
  654. .bmAttributes = USB_ENDPOINT_XFER_BULK,
  655. .ep_type = ep_bulk_in,
  656. .fifo_num = 2,
  657. },
  658. .ep[3] = {
  659. .ep = {
  660. .name = "ep3in-int",
  661. .ops = &s3c_ep_ops,
  662. .maxpacket = EP_FIFO_SIZE,
  663. },
  664. .dev = &memory,
  665. .bEndpointAddress = USB_DIR_IN | 3,
  666. .bmAttributes = USB_ENDPOINT_XFER_INT,
  667. .ep_type = ep_interrupt,
  668. .fifo_num = 3,
  669. },
  670. };
  671. /*
  672. * probe - binds to the platform device
  673. */
  674. int s3c_udc_probe(struct s3c_plat_otg_data *pdata)
  675. {
  676. struct s3c_udc *dev = &memory;
  677. int retval = 0, i;
  678. debug("%s: %p\n", __func__, pdata);
  679. dev->pdata = pdata;
  680. phy = (struct s3c_usbotg_phy *)pdata->regs_phy;
  681. reg = (struct s3c_usbotg_reg *)pdata->regs_otg;
  682. usb_phy_ctrl = pdata->usb_phy_ctrl;
  683. /* regs_otg = (void *)pdata->regs_otg; */
  684. dev->gadget.is_dualspeed = 1; /* Hack only*/
  685. dev->gadget.is_otg = 0;
  686. dev->gadget.is_a_peripheral = 0;
  687. dev->gadget.b_hnp_enable = 0;
  688. dev->gadget.a_hnp_support = 0;
  689. dev->gadget.a_alt_hnp_support = 0;
  690. the_controller = dev;
  691. for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) {
  692. dev->dma_buf[i] = memalign(CONFIG_SYS_CACHELINE_SIZE,
  693. DMA_BUFFER_SIZE);
  694. dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i];
  695. invalidate_dcache_range((unsigned long) dev->dma_buf[i],
  696. (unsigned long) (dev->dma_buf[i]
  697. + DMA_BUFFER_SIZE));
  698. }
  699. usb_ctrl = dev->dma_buf[0];
  700. usb_ctrl_dma_addr = dev->dma_addr[0];
  701. udc_reinit(dev);
  702. return retval;
  703. }
  704. int usb_gadget_handle_interrupts()
  705. {
  706. u32 intr_status = readl(&reg->gintsts);
  707. u32 gintmsk = readl(&reg->gintmsk);
  708. if (intr_status & gintmsk)
  709. return s3c_udc_irq(1, (void *)the_controller);
  710. return 0;
  711. }