da850_lowlevel.c 9.2 KB

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  1. /*
  2. * SoC-specific lowlevel code for DA850
  3. *
  4. * Copyright (C) 2011
  5. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23. */
  24. #include <common.h>
  25. #include <nand.h>
  26. #include <ns16550.h>
  27. #include <post.h>
  28. #include <asm/arch/da850_lowlevel.h>
  29. #include <asm/arch/hardware.h>
  30. #include <asm/arch/davinci_misc.h>
  31. #include <asm/arch/ddr2_defs.h>
  32. #include <asm/arch/emif_defs.h>
  33. #include <asm/arch/pll_defs.h>
  34. void davinci_enable_uart0(void)
  35. {
  36. lpsc_on(DAVINCI_LPSC_UART0);
  37. /* Bringup UART0 out of reset */
  38. REG(UART0_PWREMU_MGMT) = 0x00006001;
  39. }
  40. #if defined(CONFIG_SYS_DA850_PLL_INIT)
  41. void da850_waitloop(unsigned long loopcnt)
  42. {
  43. unsigned long i;
  44. for (i = 0; i < loopcnt; i++)
  45. asm(" NOP");
  46. }
  47. int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
  48. {
  49. if (reg == davinci_pllc0_regs)
  50. /* Unlock PLL registers. */
  51. clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
  52. /*
  53. * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
  54. * through MMR
  55. */
  56. clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC);
  57. /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
  58. clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC);
  59. /* Set PLLEN=0 => PLL BYPASS MODE */
  60. clrbits_le32(&reg->pllctl, PLLCTL_PLLEN);
  61. da850_waitloop(150);
  62. if (reg == davinci_pllc0_regs) {
  63. /*
  64. * Select the Clock Mode bit 8 as External Clock or On Chip
  65. * Oscilator
  66. */
  67. dv_maskbits(&reg->pllctl, ~PLLCTL_RES_9);
  68. setbits_le32(&reg->pllctl,
  69. (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
  70. }
  71. /* Clear PLLRST bit to reset the PLL */
  72. clrbits_le32(&reg->pllctl, PLLCTL_PLLRST);
  73. /* Disable the PLL output */
  74. setbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
  75. /* PLL initialization sequence */
  76. /*
  77. * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
  78. * power down bit
  79. */
  80. clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN);
  81. /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
  82. clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS);
  83. #if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
  84. /* program the prediv */
  85. if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
  86. writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
  87. &reg->prediv);
  88. #endif
  89. /* Program the required multiplier value in PLLM */
  90. writel(pllmult, &reg->pllm);
  91. /* program the postdiv */
  92. if (reg == davinci_pllc0_regs)
  93. writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
  94. &reg->postdiv);
  95. else
  96. writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
  97. &reg->postdiv);
  98. /*
  99. * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
  100. * no GO operation is currently in progress
  101. */
  102. while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
  103. ;
  104. if (reg == davinci_pllc0_regs) {
  105. writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, &reg->plldiv1);
  106. writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, &reg->plldiv2);
  107. writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, &reg->plldiv3);
  108. writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, &reg->plldiv4);
  109. writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, &reg->plldiv5);
  110. writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, &reg->plldiv6);
  111. writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, &reg->plldiv7);
  112. } else {
  113. writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, &reg->plldiv1);
  114. writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, &reg->plldiv2);
  115. writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, &reg->plldiv3);
  116. }
  117. /*
  118. * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
  119. * transition.
  120. */
  121. setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT);
  122. /*
  123. * Wait for the GOSTAT bit in PLLSTAT to clear to 0
  124. * (completion of phase alignment).
  125. */
  126. while ((readl(&reg->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
  127. ;
  128. /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
  129. da850_waitloop(200);
  130. /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
  131. setbits_le32(&reg->pllctl, PLLCTL_PLLRST);
  132. /* Wait for PLL to lock. See PLL spec for PLL lock time */
  133. da850_waitloop(2400);
  134. /*
  135. * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
  136. * mode
  137. */
  138. setbits_le32(&reg->pllctl, PLLCTL_PLLEN);
  139. /*
  140. * clear EMIFA and EMIFB clock source settings, let them
  141. * run off SYSCLK
  142. */
  143. if (reg == davinci_pllc0_regs)
  144. dv_maskbits(&davinci_syscfg_regs->cfgchip3,
  145. ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
  146. return 0;
  147. }
  148. #endif /* CONFIG_SYS_DA850_PLL_INIT */
  149. #if defined(CONFIG_SYS_DA850_DDR_INIT)
  150. int da850_ddr_setup(void)
  151. {
  152. unsigned long tmp;
  153. /* Enable the Clock to DDR2/mDDR */
  154. lpsc_on(DAVINCI_LPSC_DDR_EMIF);
  155. tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
  156. if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
  157. /* Begin VTP Calibration */
  158. clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
  159. clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
  160. setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
  161. clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
  162. setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
  163. /* Polling READY bit to see when VTP calibration is done */
  164. tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
  165. while ((tmp & VTP_READY) != VTP_READY)
  166. tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
  167. setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
  168. setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
  169. }
  170. setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
  171. writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
  172. if (CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT)) {
  173. /* DDR2 */
  174. clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
  175. (1 << DDR_SLEW_DDR_PDENA_BIT) |
  176. (1 << DDR_SLEW_CMOSEN_BIT));
  177. } else {
  178. /* MOBILE DDR */
  179. setbits_le32(&davinci_syscfg1_regs->ddr_slew,
  180. (1 << DDR_SLEW_DDR_PDENA_BIT) |
  181. (1 << DDR_SLEW_CMOSEN_BIT));
  182. }
  183. /*
  184. * SDRAM Configuration Register (SDCR):
  185. * First set the BOOTUNLOCK bit to make configuration bits
  186. * writeable.
  187. */
  188. setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
  189. /*
  190. * Write the new value of these bits and clear BOOTUNLOCK.
  191. * At the same time, set the TIMUNLOCK bit to allow changing
  192. * the timing registers
  193. */
  194. tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
  195. tmp &= ~DV_DDR_BOOTUNLOCK;
  196. tmp |= DV_DDR_TIMUNLOCK;
  197. writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
  198. /* write memory configuration and timing */
  199. if (!(CONFIG_SYS_DA850_DDR2_SDBCR & (1 << DV_DDR_SDCR_DDR2EN_SHIFT))) {
  200. /* MOBILE DDR only*/
  201. writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
  202. &dv_ddr2_regs_ctrl->sdbcr2);
  203. }
  204. writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
  205. writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
  206. /* clear the TIMUNLOCK bit and write the value of the CL field */
  207. tmp &= ~DV_DDR_TIMUNLOCK;
  208. writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
  209. /*
  210. * LPMODEN and MCLKSTOPEN must be set!
  211. * Without this bits set, PSC don;t switch states !!
  212. */
  213. writel(CONFIG_SYS_DA850_DDR2_SDRCR |
  214. (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
  215. (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
  216. &dv_ddr2_regs_ctrl->sdrcr);
  217. /* SyncReset the Clock to EMIF3A SDRAM */
  218. lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
  219. /* Enable the Clock to EMIF3A SDRAM */
  220. lpsc_on(DAVINCI_LPSC_DDR_EMIF);
  221. /* disable self refresh */
  222. clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
  223. DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
  224. writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
  225. return 0;
  226. }
  227. #endif /* CONFIG_SYS_DA850_DDR_INIT */
  228. __attribute__((weak))
  229. void board_gpio_init(void)
  230. {
  231. return;
  232. }
  233. int arch_cpu_init(void)
  234. {
  235. /* Unlock kick registers */
  236. writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
  237. writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
  238. dv_maskbits(&davinci_syscfg_regs->suspsrc,
  239. CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
  240. /* configure pinmux settings */
  241. if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
  242. return 1;
  243. #if defined(CONFIG_SYS_DA850_PLL_INIT)
  244. /* PLL setup */
  245. da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
  246. da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
  247. #endif
  248. /* setup CSn config */
  249. #if defined(CONFIG_SYS_DA850_CS2CFG)
  250. writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
  251. #endif
  252. #if defined(CONFIG_SYS_DA850_CS3CFG)
  253. writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
  254. #endif
  255. da8xx_configure_lpsc_items(lpsc, lpsc_size);
  256. /* GPIO setup */
  257. board_gpio_init();
  258. NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
  259. CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
  260. /*
  261. * Fix Power and Emulation Management Register
  262. * see sprufw3a.pdf page 37 Table 24
  263. */
  264. writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
  265. DAVINCI_UART_PWREMU_MGMT_UTRST),
  266. &davinci_uart2_ctrl_regs->pwremu_mgmt);
  267. #if defined(CONFIG_SYS_DA850_DDR_INIT)
  268. da850_ddr_setup();
  269. #endif
  270. return 0;
  271. }