mcffec.c 17 KB

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  1. /*
  2. * (C) Copyright 2000-2004
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2007 Freescale Semiconductor, Inc.
  6. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #include <common.h>
  27. #include <malloc.h>
  28. #include <asm/fec.h>
  29. #include <asm/immap.h>
  30. #include <command.h>
  31. #include <config.h>
  32. #include <net.h>
  33. #include <miiphy.h>
  34. #ifdef CONFIG_MCFFEC
  35. #undef ET_DEBUG
  36. #undef MII_DEBUG
  37. /* Ethernet Transmit and Receive Buffers */
  38. #define DBUF_LENGTH 1520
  39. #define TX_BUF_CNT 2
  40. #define PKT_MAXBUF_SIZE 1518
  41. #define PKT_MINBUF_SIZE 64
  42. #define PKT_MAXBLR_SIZE 1520
  43. #define LAST_PKTBUFSRX PKTBUFSRX - 1
  44. #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
  45. #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
  46. DECLARE_GLOBAL_DATA_PTR;
  47. #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
  48. struct fec_info_s fec_info[] = {
  49. #ifdef CFG_FEC0_IOBASE
  50. {
  51. 0, /* index */
  52. CFG_FEC0_IOBASE, /* io base */
  53. CFG_FEC0_PINMUX, /* gpio pin muxing */
  54. CFG_FEC0_MIIBASE, /* mii base */
  55. -1, /* phy_addr */
  56. 0, /* duplex and speed */
  57. 0, /* phy name */
  58. 0, /* phyname init */
  59. 0, /* RX BD */
  60. 0, /* TX BD */
  61. 0, /* rx Index */
  62. 0, /* tx Index */
  63. 0, /* tx buffer */
  64. 0, /* initialized flag */
  65. },
  66. #endif
  67. #ifdef CFG_FEC1_IOBASE
  68. {
  69. 1, /* index */
  70. CFG_FEC1_IOBASE, /* io base */
  71. CFG_FEC1_PINMUX, /* gpio pin muxing */
  72. CFG_FEC1_MIIBASE, /* mii base */
  73. -1, /* phy_addr */
  74. 0, /* duplex and speed */
  75. 0, /* phy name */
  76. 0, /* phy name init */
  77. 0, /* RX BD */
  78. 0, /* TX BD */
  79. 0, /* rx Index */
  80. 0, /* tx Index */
  81. 0, /* tx buffer */
  82. 0, /* initialized flag */
  83. }
  84. #endif
  85. };
  86. int fec_send(struct eth_device *dev, volatile void *packet, int length);
  87. int fec_recv(struct eth_device *dev);
  88. int fec_init(struct eth_device *dev, bd_t * bd);
  89. void fec_halt(struct eth_device *dev);
  90. void fec_reset(struct eth_device *dev);
  91. extern int fecpin_setclear(struct eth_device *dev, int setclear);
  92. #ifdef CFG_DISCOVER_PHY
  93. extern void __mii_init(void);
  94. extern uint mii_send(uint mii_cmd);
  95. extern int mii_discover_phy(struct eth_device *dev);
  96. extern int mcffec_miiphy_read(char *devname, unsigned char addr,
  97. unsigned char reg, unsigned short *value);
  98. extern int mcffec_miiphy_write(char *devname, unsigned char addr,
  99. unsigned char reg, unsigned short value);
  100. #endif
  101. void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
  102. {
  103. if ((dup_spd >> 16) == FULL) {
  104. /* Set maximum frame length */
  105. fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
  106. FEC_RCR_PROM | 0x100;
  107. fecp->tcr = FEC_TCR_FDEN;
  108. } else {
  109. /* Half duplex mode */
  110. fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
  111. FEC_RCR_MII_MODE | FEC_RCR_DRT;
  112. fecp->tcr &= ~FEC_TCR_FDEN;
  113. }
  114. if ((dup_spd & 0xFFFF) == _100BASET) {
  115. #ifdef MII_DEBUG
  116. printf("100Mbps\n");
  117. #endif
  118. bd->bi_ethspeed = 100;
  119. } else {
  120. #ifdef MII_DEBUG
  121. printf("10Mbps\n");
  122. #endif
  123. bd->bi_ethspeed = 10;
  124. }
  125. }
  126. int fec_send(struct eth_device *dev, volatile void *packet, int length)
  127. {
  128. struct fec_info_s *info = dev->priv;
  129. volatile fec_t *fecp = (fec_t *) (info->iobase);
  130. int j, rc;
  131. u16 phyStatus;
  132. miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
  133. /* section 16.9.23.3
  134. * Wait for ready
  135. */
  136. j = 0;
  137. while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
  138. (j < MCFFEC_TOUT_LOOP)) {
  139. udelay(1);
  140. j++;
  141. }
  142. if (j >= MCFFEC_TOUT_LOOP) {
  143. printf("TX not ready\n");
  144. }
  145. info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
  146. info->txbd[info->txIdx].cbd_datlen = length;
  147. info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
  148. /* Activate transmit Buffer Descriptor polling */
  149. fecp->tdar = 0x01000000; /* Descriptor polling active */
  150. #ifdef CFG_UNIFY_CACHE
  151. icache_invalid();
  152. #endif
  153. j = 0;
  154. while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
  155. (j < MCFFEC_TOUT_LOOP)) {
  156. udelay(1);
  157. j++;
  158. }
  159. if (j >= MCFFEC_TOUT_LOOP) {
  160. printf("TX timeout\n");
  161. }
  162. #ifdef ET_DEBUG
  163. printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
  164. __FILE__, __LINE__, __FUNCTION__, j,
  165. info->txbd[info->txIdx].cbd_sc,
  166. (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
  167. #endif
  168. /* return only status bits */
  169. rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
  170. info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
  171. return rc;
  172. }
  173. int fec_recv(struct eth_device *dev)
  174. {
  175. struct fec_info_s *info = dev->priv;
  176. volatile fec_t *fecp = (fec_t *) (info->iobase);
  177. int length;
  178. for (;;) {
  179. #ifdef CFG_UNIFY_CACHE
  180. icache_invalid();
  181. #endif
  182. /* section 16.9.23.2 */
  183. if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
  184. length = -1;
  185. break; /* nothing received - leave for() loop */
  186. }
  187. length = info->rxbd[info->rxIdx].cbd_datlen;
  188. if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) {
  189. printf("%s[%d] err: %x\n",
  190. __FUNCTION__, __LINE__,
  191. info->rxbd[info->rxIdx].cbd_sc);
  192. #ifdef ET_DEBUG
  193. printf("%s[%d] err: %x\n",
  194. __FUNCTION__, __LINE__,
  195. info->rxbd[info->rxIdx].cbd_sc);
  196. #endif
  197. } else {
  198. length -= 4;
  199. /* Pass the packet up to the protocol layers. */
  200. NetReceive(NetRxPackets[info->rxIdx], length);
  201. fecp->eir |= FEC_EIR_RXF;
  202. }
  203. /* Give the buffer back to the FEC. */
  204. info->rxbd[info->rxIdx].cbd_datlen = 0;
  205. /* wrap around buffer index when necessary */
  206. if (info->rxIdx == LAST_PKTBUFSRX) {
  207. info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E;
  208. info->rxIdx = 0;
  209. } else {
  210. info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
  211. info->rxIdx++;
  212. }
  213. /* Try to fill Buffer Descriptors */
  214. fecp->rdar = 0x01000000; /* Descriptor polling active */
  215. }
  216. return length;
  217. }
  218. #ifdef ET_DEBUG
  219. void dbgFecRegs(struct eth_device *dev)
  220. {
  221. struct fec_info_s *info = dev->priv;
  222. volatile fec_t *fecp = (fec_t *) (info->iobase);
  223. printf("=====\n");
  224. printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
  225. printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
  226. printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar);
  227. printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar);
  228. printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
  229. printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
  230. printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
  231. printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
  232. printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
  233. printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
  234. printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
  235. printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
  236. printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
  237. printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
  238. printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
  239. printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
  240. printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
  241. printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
  242. printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr);
  243. printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr);
  244. printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr);
  245. printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr);
  246. printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr);
  247. printf("\n");
  248. printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop,
  249. fecp->rmon_t_drop);
  250. printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets,
  251. fecp->rmon_t_packets);
  252. printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt,
  253. fecp->rmon_t_bc_pkt);
  254. printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt,
  255. fecp->rmon_t_mc_pkt);
  256. printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align,
  257. fecp->rmon_t_crc_align);
  258. printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize,
  259. fecp->rmon_t_undersize);
  260. printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize,
  261. fecp->rmon_t_oversize);
  262. printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag,
  263. fecp->rmon_t_frag);
  264. printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab,
  265. fecp->rmon_t_jab);
  266. printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col,
  267. fecp->rmon_t_col);
  268. printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64,
  269. fecp->rmon_t_p64);
  270. printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127,
  271. fecp->rmon_t_p65to127);
  272. printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255,
  273. fecp->rmon_t_p128to255);
  274. printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511,
  275. fecp->rmon_t_p256to511);
  276. printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023,
  277. fecp->rmon_t_p512to1023);
  278. printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047,
  279. fecp->rmon_t_p1024to2047);
  280. printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048,
  281. fecp->rmon_t_p_gte2048);
  282. printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets,
  283. fecp->rmon_t_octets);
  284. printf("\n");
  285. printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop,
  286. fecp->ieee_t_drop);
  287. printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok,
  288. fecp->ieee_t_frame_ok);
  289. printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col,
  290. fecp->ieee_t_1col);
  291. printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol,
  292. fecp->ieee_t_mcol);
  293. printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def,
  294. fecp->ieee_t_def);
  295. printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol,
  296. fecp->ieee_t_lcol);
  297. printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol,
  298. fecp->ieee_t_excol);
  299. printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr,
  300. fecp->ieee_t_macerr);
  301. printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr,
  302. fecp->ieee_t_cserr);
  303. printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe,
  304. fecp->ieee_t_sqe);
  305. printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc,
  306. fecp->ieee_t_fdxfc);
  307. printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok,
  308. fecp->ieee_t_octets_ok);
  309. printf("\n");
  310. printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop,
  311. fecp->rmon_r_drop);
  312. printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets,
  313. fecp->rmon_r_packets);
  314. printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt,
  315. fecp->rmon_r_bc_pkt);
  316. printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt,
  317. fecp->rmon_r_mc_pkt);
  318. printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align,
  319. fecp->rmon_r_crc_align);
  320. printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize,
  321. fecp->rmon_r_undersize);
  322. printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize,
  323. fecp->rmon_r_oversize);
  324. printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag,
  325. fecp->rmon_r_frag);
  326. printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab,
  327. fecp->rmon_r_jab);
  328. printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64,
  329. fecp->rmon_r_p64);
  330. printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127,
  331. fecp->rmon_r_p65to127);
  332. printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255,
  333. fecp->rmon_r_p128to255);
  334. printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511,
  335. fecp->rmon_r_p256to511);
  336. printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023,
  337. fecp->rmon_r_p512to1023);
  338. printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047,
  339. fecp->rmon_r_p1024to2047);
  340. printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048,
  341. fecp->rmon_r_p_gte2048);
  342. printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets,
  343. fecp->rmon_r_octets);
  344. printf("\n");
  345. printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop,
  346. fecp->ieee_r_drop);
  347. printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok,
  348. fecp->ieee_r_frame_ok);
  349. printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc,
  350. fecp->ieee_r_crc);
  351. printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align,
  352. fecp->ieee_r_align);
  353. printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr,
  354. fecp->ieee_r_macerr);
  355. printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc,
  356. fecp->ieee_r_fdxfc);
  357. printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok,
  358. fecp->ieee_r_octets_ok);
  359. printf("\n\n\n");
  360. }
  361. #endif
  362. int fec_init(struct eth_device *dev, bd_t * bd)
  363. {
  364. struct fec_info_s *info = dev->priv;
  365. volatile fec_t *fecp = (fec_t *) (info->iobase);
  366. int i;
  367. u8 *ea = NULL;
  368. fecpin_setclear(dev, 1);
  369. fec_reset(dev);
  370. #if (CONFIG_COMMANDS & CFG_CMD_MII) || defined (CONFIG_MII) || \
  371. defined (CFG_DISCOVER_PHY)
  372. mii_init();
  373. setFecDuplexSpeed(fecp, bd, info->dup_spd);
  374. #else
  375. #ifndef CFG_DISCOVER_PHY
  376. setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
  377. #endif /* ifndef CFG_DISCOVER_PHY */
  378. #endif /* CFG_CMD_MII || CONFIG_MII */
  379. /* We use strictly polling mode only */
  380. fecp->eimr = 0;
  381. /* Clear any pending interrupt */
  382. fecp->eir = 0xffffffff;
  383. /* Set station address */
  384. if ((u32) fecp == CFG_FEC0_IOBASE) {
  385. ea = &bd->bi_enetaddr[0];
  386. } else {
  387. #ifdef CFG_FEC1_IOBASE
  388. ea = &bd->bi_enet1addr[0];
  389. #endif
  390. }
  391. fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
  392. fecp->paur = (ea[4] << 24) | (ea[5] << 16);
  393. #ifdef ET_DEBUG
  394. printf("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n",
  395. ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
  396. #endif
  397. /* Clear unicast address hash table */
  398. fecp->iaur = 0;
  399. fecp->ialr = 0;
  400. /* Clear multicast address hash table */
  401. fecp->gaur = 0;
  402. fecp->galr = 0;
  403. /* Set maximum receive buffer size. */
  404. fecp->emrbr = PKT_MAXBLR_SIZE;
  405. /*
  406. * Setup Buffers and Buffer Desriptors
  407. */
  408. info->rxIdx = 0;
  409. info->txIdx = 0;
  410. /*
  411. * Setup Receiver Buffer Descriptors (13.14.24.18)
  412. * Settings:
  413. * Empty, Wrap
  414. */
  415. for (i = 0; i < PKTBUFSRX; i++) {
  416. info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
  417. info->rxbd[i].cbd_datlen = 0; /* Reset */
  418. info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
  419. }
  420. info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
  421. /*
  422. * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
  423. * Settings:
  424. * Last, Tx CRC
  425. */
  426. for (i = 0; i < TX_BUF_CNT; i++) {
  427. info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
  428. info->txbd[i].cbd_datlen = 0; /* Reset */
  429. info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
  430. }
  431. info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
  432. /* Set receive and transmit descriptor base */
  433. fecp->erdsr = (unsigned int)(&info->rxbd[0]);
  434. fecp->etdsr = (unsigned int)(&info->txbd[0]);
  435. /* Now enable the transmit and receive processing */
  436. fecp->ecr |= FEC_ECR_ETHER_EN;
  437. /* And last, try to fill Rx Buffer Descriptors */
  438. fecp->rdar = 0x01000000; /* Descriptor polling active */
  439. return 1;
  440. }
  441. void fec_reset(struct eth_device *dev)
  442. {
  443. struct fec_info_s *info = dev->priv;
  444. volatile fec_t *fecp = (fec_t *) (info->iobase);
  445. int i;
  446. fecp->ecr = FEC_ECR_RESET;
  447. for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) {
  448. udelay(1);
  449. }
  450. if (i == FEC_RESET_DELAY) {
  451. printf("FEC_RESET_DELAY timeout\n");
  452. }
  453. }
  454. void fec_halt(struct eth_device *dev)
  455. {
  456. struct fec_info_s *info = dev->priv;
  457. fec_reset(dev);
  458. fecpin_setclear(dev, 0);
  459. info->rxIdx = info->txIdx = 0;
  460. memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t));
  461. memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t));
  462. memset(info->txbuf, 0, DBUF_LENGTH);
  463. }
  464. int mcffec_initialize(bd_t * bis)
  465. {
  466. struct eth_device *dev;
  467. int i;
  468. for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
  469. dev =
  470. (struct eth_device *)memalign(CFG_CACHELINE_SIZE,
  471. sizeof *dev);
  472. if (dev == NULL)
  473. hang();
  474. memset(dev, 0, sizeof(*dev));
  475. sprintf(dev->name, "FEC%d", fec_info[i].index);
  476. dev->priv = &fec_info[i];
  477. dev->init = fec_init;
  478. dev->halt = fec_halt;
  479. dev->send = fec_send;
  480. dev->recv = fec_recv;
  481. /* setup Receive and Transmit buffer descriptor */
  482. fec_info[i].rxbd =
  483. (cbd_t *) memalign(CFG_CACHELINE_SIZE,
  484. (PKTBUFSRX * sizeof(cbd_t)));
  485. fec_info[i].txbd =
  486. (cbd_t *) memalign(CFG_CACHELINE_SIZE,
  487. (TX_BUF_CNT * sizeof(cbd_t)));
  488. fec_info[i].txbuf =
  489. (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH);
  490. #ifdef ET_DEBUG
  491. printf("rxbd %x txbd %x\n",
  492. (int)fec_info[i].rxbd, (int)fec_info[i].txbd);
  493. #endif
  494. fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32);
  495. eth_register(dev);
  496. #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
  497. miiphy_register(dev->name,
  498. mcffec_miiphy_read, mcffec_miiphy_write);
  499. #endif
  500. }
  501. /* default speed */
  502. bis->bi_ethspeed = 10;
  503. return 1;
  504. }
  505. #endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */
  506. #endif /* CONFIG_MCFFEC */